diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index 663117c6b85bf..a08d379936abd 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -995,9 +995,9 @@ static bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI, LLT Ty = MRI.getType(Reg); const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); const TargetRegisterClass *RC = - RegClassOrBank.dyn_cast(); + dyn_cast(RegClassOrBank); if (!RC) { - const RegisterBank &RB = *RegClassOrBank.get(); + const RegisterBank &RB = *cast(RegClassOrBank); RC = getRegClassForTypeOnBank(Ty, RB); if (!RC) { LLVM_DEBUG( @@ -2590,14 +2590,14 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(DefReg); - const TargetRegisterClass *DefRC - = RegClassOrBank.dyn_cast(); + const TargetRegisterClass *DefRC = + dyn_cast(RegClassOrBank); if (!DefRC) { if (!DefTy.isValid()) { LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n"); return false; } - const RegisterBank &RB = *RegClassOrBank.get(); + const RegisterBank &RB = *cast(RegClassOrBank); DefRC = getRegClassForTypeOnBank(DefTy, RB); if (!DefRC) { LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n"); @@ -4677,7 +4677,7 @@ AArch64InstructionSelector::emitCSINC(Register Dst, Register Src1, // If we used a register class, then this won't necessarily have an LLT. // Compute the size based off whether or not we have a class or bank. unsigned Size; - if (const auto *RC = RegClassOrBank.dyn_cast()) + if (const auto *RC = dyn_cast(RegClassOrBank)) Size = TRI.getRegSizeInBits(*RC); else Size = MRI.getType(Dst).getSizeInBits(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 1873251ea358b..d51d136ba4200 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -81,7 +81,7 @@ bool AMDGPUInstructionSelector::isVCC(Register Reg, auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); const TargetRegisterClass *RC = - RegClassOrBank.dyn_cast(); + dyn_cast(RegClassOrBank); if (RC) { const LLT Ty = MRI.getType(Reg); if (!Ty.isValid() || Ty.getSizeInBits() != 1) @@ -91,7 +91,7 @@ bool AMDGPUInstructionSelector::isVCC(Register Reg, RC->hasSuperClassEq(TRI.getBoolRC()); } - const RegisterBank *RB = RegClassOrBank.get(); + const RegisterBank *RB = cast(RegClassOrBank); return RB->getID() == AMDGPU::VCCRegBankID; } @@ -233,15 +233,15 @@ bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const { const RegClassOrRegBank &RegClassOrBank = MRI->getRegClassOrRegBank(DefReg); - const TargetRegisterClass *DefRC - = RegClassOrBank.dyn_cast(); + const TargetRegisterClass *DefRC = + dyn_cast(RegClassOrBank); if (!DefRC) { if (!DefTy.isValid()) { LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n"); return false; } - const RegisterBank &RB = *RegClassOrBank.get(); + const RegisterBank &RB = *cast(RegClassOrBank); DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB); if (!DefRC) { LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n"); @@ -2395,11 +2395,11 @@ const RegisterBank *AMDGPUInstructionSelector::getArtifactRegBank( Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const { const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); - if (auto *RB = RegClassOrBank.dyn_cast()) + if (auto *RB = dyn_cast(RegClassOrBank)) return RB; // Ignore the type, since we don't use vcc in artifacts. - if (auto *RC = RegClassOrBank.dyn_cast()) + if (auto *RC = dyn_cast(RegClassOrBank)) return &RBI.getRegBankFromRegClass(*RC, LLT()); return nullptr; } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 707468892d177..f76d1266f495c 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -3682,10 +3682,10 @@ const TargetRegisterClass * SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const { const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg()); - if (const RegisterBank *RB = RCOrRB.dyn_cast()) + if (const RegisterBank *RB = dyn_cast(RCOrRB)) return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB); - if (const auto *RC = RCOrRB.dyn_cast()) + if (const auto *RC = dyn_cast(RCOrRB)) return getAllocatableClass(RC); return nullptr; diff --git a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp index 39f38259a193b..df948e4407c6f 100644 --- a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp +++ b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp @@ -303,7 +303,7 @@ static uint32_t calcArraySize(const DICompositeType *CTy, uint32_t StartDim) { if (auto *Element = dyn_cast_or_null(Elements[I])) if (Element->getTag() == dwarf::DW_TAG_subrange_type) { const DISubrange *SR = cast(Element); - auto *CI = SR->getCount().dyn_cast(); + auto *CI = dyn_cast(SR->getCount()); DimSize *= CI->getSExtValue(); } } diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp index a14e9db5f7500..1a9ee3128e20d 100644 --- a/llvm/lib/Target/BPF/BTFDebug.cpp +++ b/llvm/lib/Target/BPF/BTFDebug.cpp @@ -715,7 +715,7 @@ void BTFDebug::visitArrayType(const DICompositeType *CTy, uint32_t &TypeId) { if (auto *Element = dyn_cast_or_null(Elements[I])) if (Element->getTag() == dwarf::DW_TAG_subrange_type) { const DISubrange *SR = cast(Element); - auto *CI = SR->getCount().dyn_cast(); + auto *CI = dyn_cast(SR->getCount()); int64_t Count = CI->getSExtValue(); // For struct s { int b; char c[]; }, the c[] will be represented diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index bff2356ef5fdd..1a042375d0720 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -598,14 +598,14 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { MRI->getRegClassOrRegBank(DefReg); const TargetRegisterClass *DefRC = - RegClassOrBank.dyn_cast(); + dyn_cast(RegClassOrBank); if (!DefRC) { if (!DefTy.isValid()) { LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n"); return false; } - const RegisterBank &RB = *RegClassOrBank.get(); + const RegisterBank &RB = *cast(RegClassOrBank); DefRC = getRegClassForTypeOnBank(DefTy, RB); if (!DefRC) { LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n"); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp index 3a5dda946adfb..7bffeefc788a2 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp @@ -141,8 +141,8 @@ yaml::WebAssemblyFunctionInfo::WebAssemblyFunctionInfo( for (const auto &MBB : MF) MBBs.insert(&MBB); for (auto KV : EHInfo->SrcToUnwindDest) { - auto *SrcBB = KV.first.get(); - auto *DestBB = KV.second.get(); + auto *SrcBB = cast(KV.first); + auto *DestBB = cast(KV.second); if (MBBs.count(SrcBB) && MBBs.count(DestBB)) SrcToUnwindDest[SrcBB->getNumber()] = DestBB->getNumber(); }