From 55641bb6831c13ecf60414a805ba51fee34a0793 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 11 Nov 2024 07:32:42 -0800 Subject: [PATCH 1/8] [RISCV][RegAlloc] Pre-commit test case --- .../CodeGen/RISCV/fixed-global-regalloc.ll | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll diff --git a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll b/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll new file mode 100644 index 0000000000000..f814f578bf98f --- /dev/null +++ b/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll @@ -0,0 +1,28 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc %s -mtriple=riscv64 -mattr=+reserve-x24 | FileCheck %s + +define i32 @main() { +; CHECK-LABEL: main: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd s8, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset s8, -8 +; CHECK-NEXT: li s8, 123 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ld s8, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: .cfi_restore s8 +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: ret +entry: + tail call void @llvm.write_register.i64(metadata !0, i64 123) + ret i32 0 +} + +declare void @llvm.write_register.i64(metadata, i64) #1 + +!llvm.named.register.x24 = !{!0} + +!0 = !{!"x24"} + From 3c661fe58a2fc3524dde5742529808f39c989e8f Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 11 Nov 2024 10:31:51 -0800 Subject: [PATCH 2/8] [MRI][RISCV] Account for fixed registers when determining callee saved regs --- llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 2 ++ llvm/lib/CodeGen/MachineRegisterInfo.cpp | 8 +++++++- llvm/lib/Target/M68k/M68kRegisterInfo.cpp | 2 +- llvm/lib/Target/M68k/M68kSubtarget.h | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +-- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 +- llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll | 8 -------- 8 files changed, 14 insertions(+), 15 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h index bfaa6450779ae..6b14d1476568f 100644 --- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h +++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h @@ -339,6 +339,8 @@ class TargetSubtargetInfo : public MCSubtargetInfo { // Conservatively assume such instructions exist by default. return true; } + + virtual bool isRegisterReservedByUser(Register R) const { return false; } }; } // end namespace llvm diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index fcedb302d228c..6f636a161f500 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -635,7 +635,13 @@ const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const { if (IsUpdatedCSRsInitialized) return UpdatedCSRs.data(); - return getTargetRegisterInfo()->getCalleeSavedRegs(MF); + const MCPhysReg *Regs = getTargetRegisterInfo()->getCalleeSavedRegs(MF); + + for (unsigned I = 0; Regs[I]; ++I) + if (MF->getSubtarget().isRegisterReservedByUser(Regs[I])) + MF->getRegInfo().disableCalleeSavedRegister(Regs[I]); + + return Regs; } void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef CSRs) { diff --git a/llvm/lib/Target/M68k/M68kRegisterInfo.cpp b/llvm/lib/Target/M68k/M68kRegisterInfo.cpp index 62fb72ba4fd5e..0f6b4761f2cb8 100644 --- a/llvm/lib/Target/M68k/M68kRegisterInfo.cpp +++ b/llvm/lib/Target/M68k/M68kRegisterInfo.cpp @@ -136,7 +136,7 @@ BitVector M68kRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // Registers reserved by users for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) { - if (MF.getSubtarget().isRegisterReservedByUser(Reg)) + if (MF.getSubtarget().isRegisterReservedByUser(Reg)) setBitVector(Reg); } diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h index 3fbec2f72fb86..c08a9786fb27b 100644 --- a/llvm/lib/Target/M68k/M68kSubtarget.h +++ b/llvm/lib/Target/M68k/M68kSubtarget.h @@ -107,7 +107,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo { bool isPositionIndependent() const; - bool isRegisterReservedByUser(Register R) const { + bool isRegisterReservedByUser(Register R) const override { assert(R < M68k::NUM_TARGET_REGS && "Register out of range"); return UserReservedRegister[R]; } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 831b0b30d47fc..c8c495327c383 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -19884,8 +19884,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, // reserved, if so report an error. Do the same for the return address if this // is not a tailcall. validateCCReservedRegs(RegsToPass, MF); - if (!IsTailCall && - MF.getSubtarget().isRegisterReservedByUser(RISCV::X1)) + if (!IsTailCall && MF.getSubtarget().isRegisterReservedByUser(RISCV::X1)) MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{ MF.getFunction(), "Return address register required, but has been reserved."}); diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 26195ef721db3..4b3b1d5154e9f 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -163,7 +163,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const { - return !MF.getSubtarget().isRegisterReservedByUser(PhysReg); + return !MF.getSubtarget().isRegisterReservedByUser(PhysReg); } const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index f59a3737ae76f..99edf22eb0791 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -218,7 +218,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { TargetABI == RISCVABI::ABI_ILP32 || TargetABI == RISCVABI::ABI_ILP32E; } - bool isRegisterReservedByUser(Register i) const { + bool isRegisterReservedByUser(Register i) const override { assert(i < RISCV::NUM_TARGET_REGS && "Register out of range"); return UserReservedRegister[i]; } diff --git a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll b/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll index f814f578bf98f..f1993ae142ae8 100644 --- a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll +++ b/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll @@ -4,16 +4,8 @@ define i32 @main() { ; CHECK-LABEL: main: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: sd s8, 8(sp) # 8-byte Folded Spill -; CHECK-NEXT: .cfi_offset s8, -8 ; CHECK-NEXT: li s8, 123 ; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: ld s8, 8(sp) # 8-byte Folded Reload -; CHECK-NEXT: .cfi_restore s8 -; CHECK-NEXT: addi sp, sp, 16 -; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret entry: tail call void @llvm.write_register.i64(metadata !0, i64 123) From 958aeb31c243d0c295936b46017a52342747c5df Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 11 Nov 2024 11:34:27 -0800 Subject: [PATCH 3/8] fixup! fix test checks RUN string --- .../RISCV/{fixed-global-regalloc.ll => fixed-csr.ll} | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) rename llvm/test/CodeGen/RISCV/{fixed-global-regalloc.ll => fixed-csr.ll} (78%) diff --git a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll b/llvm/test/CodeGen/RISCV/fixed-csr.ll similarity index 78% rename from llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll rename to llvm/test/CodeGen/RISCV/fixed-csr.ll index f1993ae142ae8..284d244717c19 100644 --- a/llvm/test/CodeGen/RISCV/fixed-global-regalloc.ll +++ b/llvm/test/CodeGen/RISCV/fixed-csr.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc %s -mtriple=riscv64 -mattr=+reserve-x24 | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+reserve-x24 < %s | FileCheck %s -define i32 @main() { -; CHECK-LABEL: main: +define i32 @foo() { +; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: li s8, 123 ; CHECK-NEXT: li a0, 0 From dc3a58b0e4f1ea24663ba9461e838c73c2d8a349 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 11 Nov 2024 14:02:50 -0800 Subject: [PATCH 4/8] fixup spill next register --- llvm/test/CodeGen/RISCV/fixed-csr.ll | 33 ++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/fixed-csr.ll b/llvm/test/CodeGen/RISCV/fixed-csr.ll index 284d244717c19..c3c28f3b042ee 100644 --- a/llvm/test/CodeGen/RISCV/fixed-csr.ll +++ b/llvm/test/CodeGen/RISCV/fixed-csr.ll @@ -1,20 +1,39 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x24 < %s | FileCheck %s -define i32 @foo() { +define noundef signext i32 @foo() { ; CHECK-LABEL: foo: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: li s8, 123 +; CHECK: # %bb.0: +; CHECK-NEXT: li s8, 321 ; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: ret -entry: - tail call void @llvm.write_register.i64(metadata !0, i64 123) + tail call void @llvm.write_register.i64(metadata !0, i64 321) ret i32 0 } -declare void @llvm.write_register.i64(metadata, i64) #1 +declare void @llvm.write_register.i64(metadata, i64) -!llvm.named.register.x24 = !{!0} +define noundef signext i32 @bar() { +; CHECK-LABEL: bar: +; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd s9, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset s9, -8 +; CHECK-NEXT: #APP +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: li s8, 321 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ld s9, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: .cfi_restore s9 +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: ret + tail call void asm sideeffect "", "~{x25}"() #3 + tail call void @llvm.write_register.i64(metadata !0, i64 321) + ret i32 0 +} +!llvm.named.register.x24 = !{!0} !0 = !{!"x24"} From 5af316141c2d80d06edbef375e36ab9cf1311445 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Tue, 12 Nov 2024 08:41:30 -0800 Subject: [PATCH 5/8] fixup! add m68k test --- llvm/test/CodeGen/M68k/fixed-csr.ll | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 llvm/test/CodeGen/M68k/fixed-csr.ll diff --git a/llvm/test/CodeGen/M68k/fixed-csr.ll b/llvm/test/CodeGen/M68k/fixed-csr.ll new file mode 100644 index 0000000000000..df3c4b1fddcd8 --- /dev/null +++ b/llvm/test/CodeGen/M68k/fixed-csr.ll @@ -0,0 +1,12 @@ +; RUN: not --crash llc -mtriple=m68k -mattr=+reserve-a0 < %s 2>&1 | FileCheck %s + +; CHECK: Named registers not implemented for this target +define noundef i32 @foo() { + tail call void @llvm.write_register.i32(metadata !0, i32 321) + ret i32 0 +} + +declare void @llvm.write_register.i32(metadata, i32) + +!llvm.named.register.a0 = !{!0} +!0 = !{!"a0"} From 59dc0b72d610116678368a762f5fd9f8755edbbe Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Tue, 12 Nov 2024 09:02:25 -0800 Subject: [PATCH 6/8] fixup! use callee saved register --- llvm/test/CodeGen/M68k/fixed-csr.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/M68k/fixed-csr.ll b/llvm/test/CodeGen/M68k/fixed-csr.ll index df3c4b1fddcd8..ffc6b4fb922c2 100644 --- a/llvm/test/CodeGen/M68k/fixed-csr.ll +++ b/llvm/test/CodeGen/M68k/fixed-csr.ll @@ -9,4 +9,4 @@ define noundef i32 @foo() { declare void @llvm.write_register.i32(metadata, i32) !llvm.named.register.a0 = !{!0} -!0 = !{!"a0"} +!0 = !{!"d2"} From 857380f61bd548c894fb943a259d195030b9253d Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 25 Nov 2024 14:30:46 -0800 Subject: [PATCH 7/8] fixup! fremove M68k from patch --- llvm/lib/Target/M68k/M68kRegisterInfo.cpp | 2 +- llvm/lib/Target/M68k/M68kSubtarget.h | 2 +- llvm/test/CodeGen/M68k/fixed-csr.ll | 12 ------------ 3 files changed, 2 insertions(+), 14 deletions(-) delete mode 100644 llvm/test/CodeGen/M68k/fixed-csr.ll diff --git a/llvm/lib/Target/M68k/M68kRegisterInfo.cpp b/llvm/lib/Target/M68k/M68kRegisterInfo.cpp index 0f6b4761f2cb8..62fb72ba4fd5e 100644 --- a/llvm/lib/Target/M68k/M68kRegisterInfo.cpp +++ b/llvm/lib/Target/M68k/M68kRegisterInfo.cpp @@ -136,7 +136,7 @@ BitVector M68kRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // Registers reserved by users for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) { - if (MF.getSubtarget().isRegisterReservedByUser(Reg)) + if (MF.getSubtarget().isRegisterReservedByUser(Reg)) setBitVector(Reg); } diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h index c08a9786fb27b..3fbec2f72fb86 100644 --- a/llvm/lib/Target/M68k/M68kSubtarget.h +++ b/llvm/lib/Target/M68k/M68kSubtarget.h @@ -107,7 +107,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo { bool isPositionIndependent() const; - bool isRegisterReservedByUser(Register R) const override { + bool isRegisterReservedByUser(Register R) const { assert(R < M68k::NUM_TARGET_REGS && "Register out of range"); return UserReservedRegister[R]; } diff --git a/llvm/test/CodeGen/M68k/fixed-csr.ll b/llvm/test/CodeGen/M68k/fixed-csr.ll deleted file mode 100644 index ffc6b4fb922c2..0000000000000 --- a/llvm/test/CodeGen/M68k/fixed-csr.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: not --crash llc -mtriple=m68k -mattr=+reserve-a0 < %s 2>&1 | FileCheck %s - -; CHECK: Named registers not implemented for this target -define noundef i32 @foo() { - tail call void @llvm.write_register.i32(metadata !0, i32 321) - ret i32 0 -} - -declare void @llvm.write_register.i32(metadata, i32) - -!llvm.named.register.a0 = !{!0} -!0 = !{!"d2"} From b6f1191b541ef63a1cae5b6135f26b3d435f5ca4 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Thu, 5 Dec 2024 06:51:04 -0800 Subject: [PATCH 8/8] fixup! add nounwind to test --- llvm/test/CodeGen/RISCV/fixed-csr.ll | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/fixed-csr.ll b/llvm/test/CodeGen/RISCV/fixed-csr.ll index c3c28f3b042ee..f39085132e4a2 100644 --- a/llvm/test/CodeGen/RISCV/fixed-csr.ll +++ b/llvm/test/CodeGen/RISCV/fixed-csr.ll @@ -13,21 +13,17 @@ define noundef signext i32 @foo() { declare void @llvm.write_register.i64(metadata, i64) -define noundef signext i32 @bar() { +define noundef signext i32 @bar() nounwind { ; CHECK-LABEL: bar: ; CHECK: # %bb.0: ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: sd s9, 8(sp) # 8-byte Folded Spill -; CHECK-NEXT: .cfi_offset s9, -8 ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: li s8, 321 ; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: ld s9, 8(sp) # 8-byte Folded Reload -; CHECK-NEXT: .cfi_restore s9 ; CHECK-NEXT: addi sp, sp, 16 -; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret tail call void asm sideeffect "", "~{x25}"() #3 tail call void @llvm.write_register.i64(metadata !0, i64 321)