From 7c48f4cac7347212825da78b7ec7ebed1184e6a3 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Mon, 18 Nov 2024 23:30:19 +0800 Subject: [PATCH 1/2] [InstCombine] Add pre-commit tests. NFC. --- llvm/test/Transforms/InstCombine/bit_ceil.ll | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll b/llvm/test/Transforms/InstCombine/bit_ceil.ll index 0551a5cb5e2f2..b810948090db2 100644 --- a/llvm/test/Transforms/InstCombine/bit_ceil.ll +++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll @@ -320,6 +320,23 @@ define i32 @pr91691_keep_nsw(i32 %0) { ret i32 %7 } +define i32 @test_drop_range_attr(i32 %x) { +; CHECK-LABEL: @test_drop_range_attr( +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) +; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[CTLZ]] +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 31 +; CHECK-NEXT: [[SEL:%.*]] = shl nuw i32 1, [[TMP2]] +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctlz = call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 %x, i1 false) + %sub = sub i32 32, %ctlz + %shl = shl i32 1, %sub + %dec = add i32 %x, -1 + %ult = icmp ult i32 %dec, -2 + %sel = select i1 %ult, i32 %shl, i32 1 + ret i32 %sel +} + declare i32 @llvm.ctlz.i32(i32, i1 immarg) declare i64 @llvm.ctlz.i64(i64, i1 immarg) declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) From 3ffb79c20b72b1aba90d7ff986f100f9aff0944d Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Mon, 18 Nov 2024 23:39:07 +0800 Subject: [PATCH 2/2] [InstCombine] Drop range attributes in `foldBitCeil` --- llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | 9 +++++++-- llvm/test/Transforms/InstCombine/bit_ceil.ll | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 010b77548c152..b39b7d50210c8 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -3469,7 +3469,8 @@ static bool isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0, // Note that the select is optimized away while the shift count is masked with // 31. We handle some variations of the input operand like std::bit_ceil(X + // 1). -static Instruction *foldBitCeil(SelectInst &SI, IRBuilderBase &Builder) { +static Instruction *foldBitCeil(SelectInst &SI, IRBuilderBase &Builder, + InstCombinerImpl &IC) { Type *SelType = SI.getType(); unsigned BitWidth = SelType->getScalarSizeInBits(); @@ -3504,6 +3505,10 @@ static Instruction *foldBitCeil(SelectInst &SI, IRBuilderBase &Builder) { // single hardware instruction as opposed to BitWidth - CTLZ, where BitWidth // is an integer constant. Masking with BitWidth-1 comes free on some // hardware as part of the shift instruction. + + // Drop range attributes and re-infer them in the next iteration. + cast(Ctlz)->dropPoisonGeneratingAnnotations(); + IC.addToWorklist(cast(Ctlz)); Value *Neg = Builder.CreateNeg(Ctlz); Value *Masked = Builder.CreateAnd(Neg, ConstantInt::get(SelType, BitWidth - 1)); @@ -4147,7 +4152,7 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) { if (sinkNotIntoOtherHandOfLogicalOp(SI)) return &SI; - if (Instruction *I = foldBitCeil(SI, Builder)) + if (Instruction *I = foldBitCeil(SI, Builder, *this)) return I; if (Instruction *I = foldSelectToCmp(SI)) diff --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll b/llvm/test/Transforms/InstCombine/bit_ceil.ll index b810948090db2..a2e27dfd6f64d 100644 --- a/llvm/test/Transforms/InstCombine/bit_ceil.ll +++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll @@ -322,7 +322,7 @@ define i32 @pr91691_keep_nsw(i32 %0) { define i32 @test_drop_range_attr(i32 %x) { ; CHECK-LABEL: @test_drop_range_attr( -; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[CTLZ]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 31 ; CHECK-NEXT: [[SEL:%.*]] = shl nuw i32 1, [[TMP2]]