From 99109d5388eba1e54774005ffc4828ef63d11b3f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 19 Nov 2024 16:13:08 +0000 Subject: [PATCH 1/2] [X86] Rename AVX512 VEXTRACT/INSERT??x? to VEXTRACT/INSERT??X? Use uppercase in the subvector description ("32x2" -> "32X4" etc.) - matches what we already do in VBROADCAST??X?, and we try to use uppercase for all x86 instruction mnemonics anyway (and lowercase just for the arg description suffix). --- .../X86/GISel/X86InstructionSelector.cpp | 12 +- llvm/lib/Target/X86/X86InstrAVX512.td | 206 +++++++++--------- llvm/lib/Target/X86/X86InstrInfo.cpp | 8 +- llvm/lib/Target/X86/X86ReplaceableInstrs.def | 48 ++-- llvm/lib/Target/X86/X86SchedIceLake.td | 16 +- llvm/lib/Target/X86/X86SchedSapphireRapids.td | 6 +- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 16 +- llvm/test/TableGen/x86-fold-tables.inc | 96 ++++---- llvm/test/TableGen/x86-instr-mapping.inc | 32 +-- llvm/utils/TableGen/X86ManualFoldTables.def | 24 +- llvm/utils/TableGen/X86ManualInstrMapping.def | 16 +- 11 files changed, 240 insertions(+), 240 deletions(-) diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp index d425a0d507524..ee456a11d5844 100644 --- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp @@ -1254,16 +1254,16 @@ bool X86InstructionSelector::selectExtract(MachineInstr &I, if (SrcTy.getSizeInBits() == 256 && DstTy.getSizeInBits() == 128) { if (HasVLX) - I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rri)); + I.setDesc(TII.get(X86::VEXTRACTF32X4Z256rri)); else if (HasAVX) I.setDesc(TII.get(X86::VEXTRACTF128rri)); else return false; } else if (SrcTy.getSizeInBits() == 512 && HasAVX512) { if (DstTy.getSizeInBits() == 128) - I.setDesc(TII.get(X86::VEXTRACTF32x4Zrri)); + I.setDesc(TII.get(X86::VEXTRACTF32X4Zrri)); else if (DstTy.getSizeInBits() == 256) - I.setDesc(TII.get(X86::VEXTRACTF64x4Zrri)); + I.setDesc(TII.get(X86::VEXTRACTF64X4Zrri)); else return false; } else @@ -1387,16 +1387,16 @@ bool X86InstructionSelector::selectInsert(MachineInstr &I, if (DstTy.getSizeInBits() == 256 && InsertRegTy.getSizeInBits() == 128) { if (HasVLX) - I.setDesc(TII.get(X86::VINSERTF32x4Z256rri)); + I.setDesc(TII.get(X86::VINSERTF32X4Z256rri)); else if (HasAVX) I.setDesc(TII.get(X86::VINSERTF128rri)); else return false; } else if (DstTy.getSizeInBits() == 512 && HasAVX512) { if (InsertRegTy.getSizeInBits() == 128) - I.setDesc(TII.get(X86::VINSERTF32x4Zrri)); + I.setDesc(TII.get(X86::VINSERTF32X4Zrri)); else if (InsertRegTy.getSizeInBits() == 256) - I.setDesc(TII.get(X86::VINSERTF64x4Zrri)); + I.setDesc(TII.get(X86::VINSERTF64X4Zrri)); else return false; } else diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 7adc72f8bc7d0..4094a1ba9b790 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -427,24 +427,24 @@ multiclass vinsert_for_type { let Predicates = [HasVLX] in - defm NAME # "32x4Z256" : vinsert_for_size, X86VectorVTInfo< 8, EltVT32, VR256X>, vinsert128_insert, sched>, EVEX_V256; - defm NAME # "32x4Z" : vinsert_for_size, X86VectorVTInfo<16, EltVT32, VR512>, vinsert128_insert, sched>, EVEX_V512; - defm NAME # "64x4Z" : vinsert_for_size, X86VectorVTInfo< 8, EltVT64, VR512>, vinsert256_insert, sched>, REX_W, EVEX_V512; // Even with DQI we'd like to only use these instructions for masking. let Predicates = [HasVLX, HasDQI] in - defm NAME # "64x2Z256" : vinsert_for_size_split, X86VectorVTInfo< 4, EltVT64, VR256X>, null_frag, vinsert128_insert, sched>, @@ -452,13 +452,13 @@ multiclass vinsert_for_type, X86VectorVTInfo< 8, EltVT64, VR512>, null_frag, vinsert128_insert, sched>, REX_W, EVEX_V512; - defm NAME # "32x8Z" : vinsert_for_size_split, X86VectorVTInfo<16, EltVT32, VR512>, null_frag, vinsert256_insert, sched>, @@ -472,47 +472,47 @@ defm VINSERTI : vinsert_for_type; // Codegen pattern with the alternative types, // Even with AVX512DQ we'll still use these for unmasked operations. -defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info, +defm : vinsert_for_size_lowering<"VINSERTF32X4Z256", v2f64x_info, v4f64x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info, +defm : vinsert_for_size_lowering<"VINSERTI32X4Z256", v2i64x_info, v4i64x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info, +defm : vinsert_for_size_lowering<"VINSERTF32X4Z", v2f64x_info, v8f64_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info, +defm : vinsert_for_size_lowering<"VINSERTI32X4Z", v2i64x_info, v8i64_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info, +defm : vinsert_for_size_lowering<"VINSERTF64X4Z", v8f32x_info, v16f32_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info, +defm : vinsert_for_size_lowering<"VINSERTI64X4Z", v8i32x_info, v16i32_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; // Codegen pattern with the alternative types insert VEC128 into VEC256 -defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info, +defm : vinsert_for_size_lowering<"VINSERTI32X4Z256", v8i16x_info, v16i16x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info, +defm : vinsert_for_size_lowering<"VINSERTI32X4Z256", v16i8x_info, v32i8x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v8f16x_info, v16f16x_info, +defm : vinsert_for_size_lowering<"VINSERTF32X4Z256", v8f16x_info, v16f16x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v8bf16x_info, v16bf16x_info, +defm : vinsert_for_size_lowering<"VINSERTF32X4Z256", v8bf16x_info, v16bf16x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; // Codegen pattern with the alternative types insert VEC128 into VEC512 -defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info, +defm : vinsert_for_size_lowering<"VINSERTI32X4Z", v8i16x_info, v32i16_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info, +defm : vinsert_for_size_lowering<"VINSERTI32X4Z", v16i8x_info, v64i8_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v8f16x_info, v32f16_info, +defm : vinsert_for_size_lowering<"VINSERTF32X4Z", v8f16x_info, v32f16_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v8bf16x_info, v32bf16_info, +defm : vinsert_for_size_lowering<"VINSERTF32X4Z", v8bf16x_info, v32bf16_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; // Codegen pattern with the alternative types insert VEC256 into VEC512 -defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info, +defm : vinsert_for_size_lowering<"VINSERTI64X4Z", v16i16x_info, v32i16_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info, +defm : vinsert_for_size_lowering<"VINSERTI64X4Z", v32i8x_info, v64i8_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v16f16x_info, v32f16_info, +defm : vinsert_for_size_lowering<"VINSERTF64X4Z", v16f16x_info, v32f16_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; -defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v16bf16x_info, v32bf16_info, +defm : vinsert_for_size_lowering<"VINSERTF64X4Z", v16bf16x_info, v32bf16_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; @@ -568,81 +568,81 @@ let Predicates = p in { } } -defm : vinsert_for_mask_cast<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info, +defm : vinsert_for_mask_cast<"VINSERTF32X4Z256", v2f64x_info, v4f64x_info, v8f32x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v4f32x_info, v8f32x_info, +defm : vinsert_for_mask_cast<"VINSERTF64X2Z256", v4f32x_info, v8f32x_info, v4f64x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; -defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info, +defm : vinsert_for_mask_cast<"VINSERTI32X4Z256", v2i64x_info, v4i64x_info, v8i32x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info, +defm : vinsert_for_mask_cast<"VINSERTI32X4Z256", v8i16x_info, v16i16x_info, v8i32x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info, +defm : vinsert_for_mask_cast<"VINSERTI32X4Z256", v16i8x_info, v32i8x_info, v8i32x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>; -defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v4i32x_info, v8i32x_info, +defm : vinsert_for_mask_cast<"VINSERTF64X2Z256", v4i32x_info, v8i32x_info, v4i64x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; -defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v8i16x_info, v16i16x_info, +defm : vinsert_for_mask_cast<"VINSERTF64X2Z256", v8i16x_info, v16i16x_info, v4i64x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; -defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v16i8x_info, v32i8x_info, +defm : vinsert_for_mask_cast<"VINSERTF64X2Z256", v16i8x_info, v32i8x_info, v4i64x_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>; -defm : vinsert_for_mask_cast<"VINSERTF32x4Z", v2f64x_info, v8f64_info, +defm : vinsert_for_mask_cast<"VINSERTF32X4Z", v2f64x_info, v8f64_info, v16f32_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_mask_cast<"VINSERTF64x2Z", v4f32x_info, v16f32_info, +defm : vinsert_for_mask_cast<"VINSERTF64X2Z", v4f32x_info, v16f32_info, v8f64_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasDQI]>; -defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v2i64x_info, v8i64_info, +defm : vinsert_for_mask_cast<"VINSERTI32X4Z", v2i64x_info, v8i64_info, v16i32_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v8i16x_info, v32i16_info, +defm : vinsert_for_mask_cast<"VINSERTI32X4Z", v8i16x_info, v32i16_info, v16i32_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v16i8x_info, v64i8_info, +defm : vinsert_for_mask_cast<"VINSERTI32X4Z", v16i8x_info, v64i8_info, v16i32_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>; -defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v4i32x_info, v16i32_info, +defm : vinsert_for_mask_cast<"VINSERTI64X2Z", v4i32x_info, v16i32_info, v8i64_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasDQI]>; -defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v8i16x_info, v32i16_info, +defm : vinsert_for_mask_cast<"VINSERTI64X2Z", v8i16x_info, v32i16_info, v8i64_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasDQI]>; -defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v16i8x_info, v64i8_info, +defm : vinsert_for_mask_cast<"VINSERTI64X2Z", v16i8x_info, v64i8_info, v8i64_info, vinsert128_insert, INSERT_get_vinsert128_imm, [HasDQI]>; -defm : vinsert_for_mask_cast<"VINSERTF32x8Z", v4f64x_info, v8f64_info, +defm : vinsert_for_mask_cast<"VINSERTF32X8Z", v4f64x_info, v8f64_info, v16f32_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasDQI]>; -defm : vinsert_for_mask_cast<"VINSERTF64x4Z", v8f32x_info, v16f32_info, +defm : vinsert_for_mask_cast<"VINSERTF64X4Z", v8f32x_info, v16f32_info, v8f64_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; -defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v4i64x_info, v8i64_info, +defm : vinsert_for_mask_cast<"VINSERTI32X8Z", v4i64x_info, v8i64_info, v16i32_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasDQI]>; -defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v16i16x_info, v32i16_info, +defm : vinsert_for_mask_cast<"VINSERTI32X8Z", v16i16x_info, v32i16_info, v16i32_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasDQI]>; -defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v32i8x_info, v64i8_info, +defm : vinsert_for_mask_cast<"VINSERTI32X8Z", v32i8x_info, v64i8_info, v16i32_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasDQI]>; -defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v8i32x_info, v16i32_info, +defm : vinsert_for_mask_cast<"VINSERTI64X4Z", v8i32x_info, v16i32_info, v8i64_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; -defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v16i16x_info, v32i16_info, +defm : vinsert_for_mask_cast<"VINSERTI64X4Z", v16i16x_info, v32i16_info, v8i64_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; -defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v32i8x_info, v64i8_info, +defm : vinsert_for_mask_cast<"VINSERTI64X4Z", v32i8x_info, v64i8_info, v8i64_info, vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>; @@ -732,19 +732,19 @@ multiclass vextract_for_type { let Predicates = [HasAVX512] in { - defm NAME # "32x4Z" : vextract_for_size, X86VectorVTInfo< 4, EltVT32, VR128X>, vextract128_extract, SchedRR, SchedMR>, EVEX_V512, EVEX_CD8<32, CD8VT4>; - defm NAME # "64x4Z" : vextract_for_size, X86VectorVTInfo< 4, EltVT64, VR256X>, vextract256_extract, SchedRR, SchedMR>, REX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; } let Predicates = [HasVLX] in - defm NAME # "32x4Z256" : vextract_for_size, X86VectorVTInfo< 4, EltVT32, VR128X>, vextract128_extract, SchedRR, SchedMR>, @@ -752,7 +752,7 @@ multiclass vextract_for_type, X86VectorVTInfo< 2, EltVT64, VR128X>, null_frag, vextract128_extract, SchedRR, SchedMR>, @@ -760,12 +760,12 @@ multiclass vextract_for_type, X86VectorVTInfo< 2, EltVT64, VR128X>, null_frag, vextract128_extract, SchedRR, SchedMR>, REX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>; - defm NAME # "32x8Z" : vextract_for_size_split, X86VectorVTInfo< 8, EltVT32, VR256X>, null_frag, vextract256_extract, SchedRR, SchedMR>, @@ -779,48 +779,48 @@ defm VEXTRACTI : vextract_for_type; -defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info, +defm : vextract_for_size_lowering<"VEXTRACTI32X4Z", v8i64_info, v2i64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info, +defm : vextract_for_size_lowering<"VEXTRACTF64X4Z", v16f32_info, v8f32x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info, +defm : vextract_for_size_lowering<"VEXTRACTI64X4Z", v16i32_info, v8i32x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info, +defm : vextract_for_size_lowering<"VEXTRACTF32X4Z256", v4f64x_info, v2f64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; -defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info, +defm : vextract_for_size_lowering<"VEXTRACTI32X4Z256", v4i64x_info, v2i64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; // Codegen pattern with the alternative types extract VEC128 from VEC256 -defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v16i16x_info, v8i16x_info, +defm : vextract_for_size_lowering<"VEXTRACTI32X4Z256", v16i16x_info, v8i16x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; -defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v32i8x_info, v16i8x_info, +defm : vextract_for_size_lowering<"VEXTRACTI32X4Z256", v32i8x_info, v16i8x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; -defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v16f16x_info, v8f16x_info, +defm : vextract_for_size_lowering<"VEXTRACTF32X4Z256", v16f16x_info, v8f16x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; -defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v16bf16x_info, v8bf16x_info, +defm : vextract_for_size_lowering<"VEXTRACTF32X4Z256", v16bf16x_info, v8bf16x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; // Codegen pattern with the alternative types extract VEC128 from VEC512 -defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info, +defm : vextract_for_size_lowering<"VEXTRACTI32X4Z", v32i16_info, v8i16x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info, +defm : vextract_for_size_lowering<"VEXTRACTI32X4Z", v64i8_info, v16i8x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v32f16_info, v8f16x_info, +defm : vextract_for_size_lowering<"VEXTRACTF32X4Z", v32f16_info, v8f16x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v32bf16_info, v8bf16x_info, +defm : vextract_for_size_lowering<"VEXTRACTF32X4Z", v32bf16_info, v8bf16x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; // Codegen pattern with the alternative types extract VEC256 from VEC512 -defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info, +defm : vextract_for_size_lowering<"VEXTRACTI64X4Z", v32i16_info, v16i16x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info, +defm : vextract_for_size_lowering<"VEXTRACTI64X4Z", v64i8_info, v32i8x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v32f16_info, v16f16x_info, +defm : vextract_for_size_lowering<"VEXTRACTF64X4Z", v32f16_info, v16f16x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; -defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v32bf16_info, v16bf16x_info, +defm : vextract_for_size_lowering<"VEXTRACTF64X4Z", v32bf16_info, v16bf16x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; @@ -861,31 +861,31 @@ def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))), // smaller extract to enable EVEX->VEX. let Predicates = [HasVLX] in { def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))), - (v2i64 (VEXTRACTI32x4Z256rri + (v2i64 (VEXTRACTI32X4Z256rri (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)), (iPTR 1)))>; def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))), - (v2f64 (VEXTRACTF32x4Z256rri + (v2f64 (VEXTRACTF32X4Z256rri (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)), (iPTR 1)))>; def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))), - (v4i32 (VEXTRACTI32x4Z256rri + (v4i32 (VEXTRACTI32X4Z256rri (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)), (iPTR 1)))>; def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))), - (v4f32 (VEXTRACTF32x4Z256rri + (v4f32 (VEXTRACTF32X4Z256rri (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)), (iPTR 1)))>; def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))), - (v8i16 (VEXTRACTI32x4Z256rri + (v8i16 (VEXTRACTI32X4Z256rri (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)), (iPTR 1)))>; def : Pat<(v8f16 (extract_subvector (v32f16 VR512:$src), (iPTR 8))), - (v8f16 (VEXTRACTF32x4Z256rri + (v8f16 (VEXTRACTF32X4Z256rri (v16f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_ymm)), (iPTR 1)))>; def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))), - (v16i8 (VEXTRACTI32x4Z256rri + (v16i8 (VEXTRACTI32X4Z256rri (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)), (iPTR 1)))>; } @@ -919,81 +919,81 @@ let Predicates = p in { } } -defm : vextract_for_mask_cast<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info, +defm : vextract_for_mask_cast<"VEXTRACTF32X4Z256", v4f64x_info, v2f64x_info, v4f32x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; -defm : vextract_for_mask_cast<"VEXTRACTF64x2Z256", v8f32x_info, v4f32x_info, +defm : vextract_for_mask_cast<"VEXTRACTF64X2Z256", v8f32x_info, v4f32x_info, v2f64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X4Z256", v4i64x_info, v2i64x_info, v4i32x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v16i16x_info, v8i16x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X4Z256", v16i16x_info, v8i16x_info, v4i32x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x4Z256", v32i8x_info, v16i8x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X4Z256", v32i8x_info, v16i8x_info, v4i32x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v8i32x_info, v4i32x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X2Z256", v8i32x_info, v4i32x_info, v2i64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v16i16x_info, v8i16x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X2Z256", v16i16x_info, v8i16x_info, v2i64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x2Z256", v32i8x_info, v16i8x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X2Z256", v32i8x_info, v16i8x_info, v2i64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasDQI, HasVLX]>; -defm : vextract_for_mask_cast<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info, +defm : vextract_for_mask_cast<"VEXTRACTF32X4Z", v8f64_info, v2f64x_info, v4f32x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; -defm : vextract_for_mask_cast<"VEXTRACTF64x2Z", v16f32_info, v4f32x_info, +defm : vextract_for_mask_cast<"VEXTRACTF64X2Z", v16f32_info, v4f32x_info, v2f64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasDQI]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X4Z", v8i64_info, v2i64x_info, v4i32x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X4Z", v32i16_info, v8i16x_info, v4i32x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X4Z", v64i8_info, v16i8x_info, v4i32x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v16i32_info, v4i32x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X2Z", v16i32_info, v4i32x_info, v2i64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasDQI]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v32i16_info, v8i16x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X2Z", v32i16_info, v8i16x_info, v2i64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasDQI]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x2Z", v64i8_info, v16i8x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X2Z", v64i8_info, v16i8x_info, v2i64x_info, vextract128_extract, EXTRACT_get_vextract128_imm, [HasDQI]>; -defm : vextract_for_mask_cast<"VEXTRACTF32x8Z", v8f64_info, v4f64x_info, +defm : vextract_for_mask_cast<"VEXTRACTF32X8Z", v8f64_info, v4f64x_info, v8f32x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasDQI]>; -defm : vextract_for_mask_cast<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info, +defm : vextract_for_mask_cast<"VEXTRACTF64X4Z", v16f32_info, v8f32x_info, v4f64x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v8i64_info, v4i64x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X8Z", v8i64_info, v4i64x_info, v8i32x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasDQI]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v32i16_info, v16i16x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X8Z", v32i16_info, v16i16x_info, v8i32x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasDQI]>; -defm : vextract_for_mask_cast<"VEXTRACTI32x8Z", v64i8_info, v32i8x_info, +defm : vextract_for_mask_cast<"VEXTRACTI32X8Z", v64i8_info, v32i8x_info, v8i32x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasDQI]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X4Z", v16i32_info, v8i32x_info, v4i64x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X4Z", v32i16_info, v16i16x_info, v4i64x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; -defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info, +defm : vextract_for_mask_cast<"VEXTRACTI64X4Z", v64i8_info, v32i8x_info, v4i64x_info, vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 8551531b1b267..7707965d20037 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -6293,16 +6293,16 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { get(X86::VBROADCASTF64X4Zrm), X86::sub_ymm); case X86::VMOVAPSZ128mr_NOVLX: return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr), - get(X86::VEXTRACTF32x4Zmri), X86::sub_xmm); + get(X86::VEXTRACTF32X4Zmri), X86::sub_xmm); case X86::VMOVUPSZ128mr_NOVLX: return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr), - get(X86::VEXTRACTF32x4Zmri), X86::sub_xmm); + get(X86::VEXTRACTF32X4Zmri), X86::sub_xmm); case X86::VMOVAPSZ256mr_NOVLX: return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr), - get(X86::VEXTRACTF64x4Zmri), X86::sub_ymm); + get(X86::VEXTRACTF64X4Zmri), X86::sub_ymm); case X86::VMOVUPSZ256mr_NOVLX: return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr), - get(X86::VEXTRACTF64x4Zmri), X86::sub_ymm); + get(X86::VEXTRACTF64X4Zmri), X86::sub_ymm); case X86::MOV32ri64: { Register Reg = MIB.getReg(0); Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit); diff --git a/llvm/lib/Target/X86/X86ReplaceableInstrs.def b/llvm/lib/Target/X86/X86ReplaceableInstrs.def index 9deb7a8bdacb8..fe7295548fe45 100644 --- a/llvm/lib/Target/X86/X86ReplaceableInstrs.def +++ b/llvm/lib/Target/X86/X86ReplaceableInstrs.def @@ -110,30 +110,30 @@ ENTRY(VBROADCASTSDZ256rr, VBROADCASTSDZ256rr, VPBROADCASTQZ256rr) ENTRY(VBROADCASTSDZ256rm, VBROADCASTSDZ256rm, VPBROADCASTQZ256rm) ENTRY(VBROADCASTSDZrr, VBROADCASTSDZrr, VPBROADCASTQZrr) ENTRY(VBROADCASTSDZrm, VBROADCASTSDZrm, VPBROADCASTQZrm) -ENTRY(VINSERTF32x4Zrri, VINSERTF32x4Zrri, VINSERTI32x4Zrri) -ENTRY(VINSERTF32x4Zrmi, VINSERTF32x4Zrmi, VINSERTI32x4Zrmi) -ENTRY(VINSERTF32x8Zrri, VINSERTF32x8Zrri, VINSERTI32x8Zrri) -ENTRY(VINSERTF32x8Zrmi, VINSERTF32x8Zrmi, VINSERTI32x8Zrmi) -ENTRY(VINSERTF64x2Zrri, VINSERTF64x2Zrri, VINSERTI64x2Zrri) -ENTRY(VINSERTF64x2Zrmi, VINSERTF64x2Zrmi, VINSERTI64x2Zrmi) -ENTRY(VINSERTF64x4Zrri, VINSERTF64x4Zrri, VINSERTI64x4Zrri) -ENTRY(VINSERTF64x4Zrmi, VINSERTF64x4Zrmi, VINSERTI64x4Zrmi) -ENTRY(VINSERTF32x4Z256rri, VINSERTF32x4Z256rri, VINSERTI32x4Z256rri) -ENTRY(VINSERTF32x4Z256rmi, VINSERTF32x4Z256rmi, VINSERTI32x4Z256rmi) -ENTRY(VINSERTF64x2Z256rri, VINSERTF64x2Z256rri, VINSERTI64x2Z256rri) -ENTRY(VINSERTF64x2Z256rmi, VINSERTF64x2Z256rmi, VINSERTI64x2Z256rmi) -ENTRY(VEXTRACTF32x4Zrri, VEXTRACTF32x4Zrri, VEXTRACTI32x4Zrri) -ENTRY(VEXTRACTF32x4Zmri, VEXTRACTF32x4Zmri, VEXTRACTI32x4Zmri) -ENTRY(VEXTRACTF32x8Zrri, VEXTRACTF32x8Zrri, VEXTRACTI32x8Zrri) -ENTRY(VEXTRACTF32x8Zmri, VEXTRACTF32x8Zmri, VEXTRACTI32x8Zmri) -ENTRY(VEXTRACTF64x2Zrri, VEXTRACTF64x2Zrri, VEXTRACTI64x2Zrri) -ENTRY(VEXTRACTF64x2Zmri, VEXTRACTF64x2Zmri, VEXTRACTI64x2Zmri) -ENTRY(VEXTRACTF64x4Zrri, VEXTRACTF64x4Zrri, VEXTRACTI64x4Zrri) -ENTRY(VEXTRACTF64x4Zmri, VEXTRACTF64x4Zmri, VEXTRACTI64x4Zmri) -ENTRY(VEXTRACTF32x4Z256rri, VEXTRACTF32x4Z256rri, VEXTRACTI32x4Z256rri) -ENTRY(VEXTRACTF32x4Z256mri, VEXTRACTF32x4Z256mri, VEXTRACTI32x4Z256mri) -ENTRY(VEXTRACTF64x2Z256rri, VEXTRACTF64x2Z256rri, VEXTRACTI64x2Z256rri) -ENTRY(VEXTRACTF64x2Z256mri, VEXTRACTF64x2Z256mri, VEXTRACTI64x2Z256mri) +ENTRY(VINSERTF32X4Zrri, VINSERTF32X4Zrri, VINSERTI32X4Zrri) +ENTRY(VINSERTF32X4Zrmi, VINSERTF32X4Zrmi, VINSERTI32X4Zrmi) +ENTRY(VINSERTF32X8Zrri, VINSERTF32X8Zrri, VINSERTI32X8Zrri) +ENTRY(VINSERTF32X8Zrmi, VINSERTF32X8Zrmi, VINSERTI32X8Zrmi) +ENTRY(VINSERTF64X2Zrri, VINSERTF64X2Zrri, VINSERTI64X2Zrri) +ENTRY(VINSERTF64X2Zrmi, VINSERTF64X2Zrmi, VINSERTI64X2Zrmi) +ENTRY(VINSERTF64X4Zrri, VINSERTF64X4Zrri, VINSERTI64X4Zrri) +ENTRY(VINSERTF64X4Zrmi, VINSERTF64X4Zrmi, VINSERTI64X4Zrmi) +ENTRY(VINSERTF32X4Z256rri, VINSERTF32X4Z256rri, VINSERTI32X4Z256rri) +ENTRY(VINSERTF32X4Z256rmi, VINSERTF32X4Z256rmi, VINSERTI32X4Z256rmi) +ENTRY(VINSERTF64X2Z256rri, VINSERTF64X2Z256rri, VINSERTI64X2Z256rri) +ENTRY(VINSERTF64X2Z256rmi, VINSERTF64X2Z256rmi, VINSERTI64X2Z256rmi) +ENTRY(VEXTRACTF32X4Zrri, VEXTRACTF32X4Zrri, VEXTRACTI32X4Zrri) +ENTRY(VEXTRACTF32X4Zmri, VEXTRACTF32X4Zmri, VEXTRACTI32X4Zmri) +ENTRY(VEXTRACTF32X8Zrri, VEXTRACTF32X8Zrri, VEXTRACTI32X8Zrri) +ENTRY(VEXTRACTF32X8Zmri, VEXTRACTF32X8Zmri, VEXTRACTI32X8Zmri) +ENTRY(VEXTRACTF64X2Zrri, VEXTRACTF64X2Zrri, VEXTRACTI64X2Zrri) +ENTRY(VEXTRACTF64X2Zmri, VEXTRACTF64X2Zmri, VEXTRACTI64X2Zmri) +ENTRY(VEXTRACTF64X4Zrri, VEXTRACTF64X4Zrri, VEXTRACTI64X4Zrri) +ENTRY(VEXTRACTF64X4Zmri, VEXTRACTF64X4Zmri, VEXTRACTI64X4Zmri) +ENTRY(VEXTRACTF32X4Z256rri, VEXTRACTF32X4Z256rri, VEXTRACTI32X4Z256rri) +ENTRY(VEXTRACTF32X4Z256mri, VEXTRACTF32X4Z256mri, VEXTRACTI32X4Z256mri) +ENTRY(VEXTRACTF64X2Z256rri, VEXTRACTF64X2Z256rri, VEXTRACTI64X2Z256rri) +ENTRY(VEXTRACTF64X2Z256mri, VEXTRACTF64X2Z256mri, VEXTRACTI64X2Z256mri) ENTRY(VPERMILPSmi, VPERMILPSmi, VPSHUFDmi) ENTRY(VPERMILPSri, VPERMILPSri, VPSHUFDri) ENTRY(VPERMILPSZ128mi, VPERMILPSZ128mi, VPSHUFDZ128mi) diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td index 8910b88d4cbd5..48be485176c3f 100644 --- a/llvm/lib/Target/X86/X86SchedIceLake.td +++ b/llvm/lib/Target/X86/X86SchedIceLake.td @@ -1591,14 +1591,14 @@ def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd], "VBROADCASTI64X4Zrm(b?)", "VBROADCASTSD(Z|Z256)rm(b?)", "VBROADCASTSS(Z|Z256)rm(b?)", - "VINSERTF32x4(Z|Z256)rm(b?)", - "VINSERTF32x8Zrm(b?)", - "VINSERTF64x2(Z|Z256)rm(b?)", - "VINSERTF64x4Zrm(b?)", - "VINSERTI32x4(Z|Z256)rm(b?)", - "VINSERTI32x8Zrm(b?)", - "VINSERTI64x2(Z|Z256)rm(b?)", - "VINSERTI64x4Zrm(b?)", + "VINSERTF32X4(Z|Z256)rm(b?)", + "VINSERTF32X8Zrm(b?)", + "VINSERTF64X2(Z|Z256)rm(b?)", + "VINSERTF64X4Zrm(b?)", + "VINSERTI32X4(Z|Z256)rm(b?)", + "VINSERTI32X8Zrm(b?)", + "VINSERTI64X2(Z|Z256)rm(b?)", + "VINSERTI64X4Zrm(b?)", "VMOVAPD(Z|Z256)rm(b?)", "VMOVAPS(Z|Z256)rm(b?)", "VMOVDDUP(Z|Z256)rm(b?)", diff --git a/llvm/lib/Target/X86/X86SchedSapphireRapids.td b/llvm/lib/Target/X86/X86SchedSapphireRapids.td index 6f3130ee58479..4344a48a52628 100644 --- a/llvm/lib/Target/X86/X86SchedSapphireRapids.td +++ b/llvm/lib/Target/X86/X86SchedSapphireRapids.td @@ -1666,8 +1666,8 @@ def : InstRW<[SPRWriteResGroup131], (instregex "^VBROADCAST(F|I)32X(8|2)Zrmk(z?) "^VMOVDQ(A|U)(32|64)Zrmk(z?)$", "^VPBROADCAST(D|Q)Zrmk(z?)$")>; def : InstRW<[SPRWriteResGroup131, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>; -def : InstRW<[SPRWriteResGroup131, ReadAfterVecYLd], (instregex "^VINSERT(F|I)(32|64)x4Zrmi((k|kz)?)$", - "^VINSERT(F|I)(32x8|64x2)Zrmi((k|kz)?)$", +def : InstRW<[SPRWriteResGroup131, ReadAfterVecYLd], (instregex "^VINSERT(F|I)(32|64)X4Zrmi((k|kz)?)$", + "^VINSERT(F|I)(32X8|64X2)Zrmi((k|kz)?)$", "^VP(ADD|SUB)(B|D|Q|W)Zrm$", "^VP(ADD|SUB)(D|Q)Zrm(b|k|kz)$", "^VP(ADD|SUB)(D|Q)Zrmbk(z?)$", @@ -2710,7 +2710,7 @@ def : InstRW<[SPRWriteResGroup262], (instregex "^VBROADCAST(F|I)32X(2|4)Z256rmk( "^VMOVDQ(A|U)(32|64)Z256rmk(z?)$", "^VPBROADCAST(D|Q)Z256rmk(z?)$")>; def : InstRW<[SPRWriteResGroup262, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rmi$", - "^VINSERT(F|I)(32x4|64x2)Z256rmi((k|kz)?)$", + "^VINSERT(F|I)(32X4|64X2)Z256rmi((k|kz)?)$", "^VP(ADD|SUB)(B|D|Q|W)(Y|Z256)rm$", "^VP(ADD|SUB)(D|Q)Z256rm(b|k|kz)$", "^VP(ADD|SUB)(D|Q)Z256rmbk(z?)$", diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 7ec725680ca31..550edaa05f7ba 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -1562,14 +1562,14 @@ def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd], "VBROADCASTI64X4Zrm(b?)", "VBROADCASTSD(Z|Z256)rm(b?)", "VBROADCASTSS(Z|Z256)rm(b?)", - "VINSERTF32x4(Z|Z256)rm(b?)", - "VINSERTF32x8Zrm(b?)", - "VINSERTF64x2(Z|Z256)rm(b?)", - "VINSERTF64x4Zrm(b?)", - "VINSERTI32x4(Z|Z256)rm(b?)", - "VINSERTI32x8Zrm(b?)", - "VINSERTI64x2(Z|Z256)rm(b?)", - "VINSERTI64x4Zrm(b?)", + "VINSERTF32X4(Z|Z256)rm(b?)", + "VINSERTF32X8Zrm(b?)", + "VINSERTF64X2(Z|Z256)rm(b?)", + "VINSERTF64X4Zrm(b?)", + "VINSERTI32X4(Z|Z256)rm(b?)", + "VINSERTI32X8Zrm(b?)", + "VINSERTI64X2(Z|Z256)rm(b?)", + "VINSERTI64X4Zrm(b?)", "VMOVAPD(Z|Z256)rm(b?)", "VMOVAPS(Z|Z256)rm(b?)", "VMOVDDUP(Z|Z256)rm(b?)", diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index c7fc7834b401a..621e9e0abeb28 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -487,19 +487,19 @@ static const X86FoldTableEntry Table0[] = { {X86::VCVTPS2PHZ256rr, X86::VCVTPS2PHZ256mr, TB_FOLDED_STORE}, {X86::VCVTPS2PHZrr, X86::VCVTPS2PHZmr, TB_FOLDED_STORE}, {X86::VEXTRACTF128rri, X86::VEXTRACTF128mri, TB_FOLDED_STORE}, - {X86::VEXTRACTF32x4Z256rri, X86::VEXTRACTF32x4Z256mri, TB_FOLDED_STORE}, - {X86::VEXTRACTF32x4Zrri, X86::VEXTRACTF32x4Zmri, TB_FOLDED_STORE}, - {X86::VEXTRACTF32x8Zrri, X86::VEXTRACTF32x8Zmri, TB_FOLDED_STORE}, - {X86::VEXTRACTF64x2Z256rri, X86::VEXTRACTF64x2Z256mri, TB_FOLDED_STORE}, - {X86::VEXTRACTF64x2Zrri, X86::VEXTRACTF64x2Zmri, TB_FOLDED_STORE}, - {X86::VEXTRACTF64x4Zrri, X86::VEXTRACTF64x4Zmri, TB_FOLDED_STORE}, + {X86::VEXTRACTF32X4Z256rri, X86::VEXTRACTF32X4Z256mri, TB_FOLDED_STORE}, + {X86::VEXTRACTF32X4Zrri, X86::VEXTRACTF32X4Zmri, TB_FOLDED_STORE}, + {X86::VEXTRACTF32X8Zrri, X86::VEXTRACTF32X8Zmri, TB_FOLDED_STORE}, + {X86::VEXTRACTF64X2Z256rri, X86::VEXTRACTF64X2Z256mri, TB_FOLDED_STORE}, + {X86::VEXTRACTF64X2Zrri, X86::VEXTRACTF64X2Zmri, TB_FOLDED_STORE}, + {X86::VEXTRACTF64X4Zrri, X86::VEXTRACTF64X4Zmri, TB_FOLDED_STORE}, {X86::VEXTRACTI128rri, X86::VEXTRACTI128mri, TB_FOLDED_STORE}, - {X86::VEXTRACTI32x4Z256rri, X86::VEXTRACTI32x4Z256mri, TB_FOLDED_STORE}, - {X86::VEXTRACTI32x4Zrri, X86::VEXTRACTI32x4Zmri, TB_FOLDED_STORE}, - {X86::VEXTRACTI32x8Zrri, X86::VEXTRACTI32x8Zmri, TB_FOLDED_STORE}, - {X86::VEXTRACTI64x2Z256rri, X86::VEXTRACTI64x2Z256mri, TB_FOLDED_STORE}, - {X86::VEXTRACTI64x2Zrri, X86::VEXTRACTI64x2Zmri, TB_FOLDED_STORE}, - {X86::VEXTRACTI64x4Zrri, X86::VEXTRACTI64x4Zmri, TB_FOLDED_STORE}, + {X86::VEXTRACTI32X4Z256rri, X86::VEXTRACTI32X4Z256mri, TB_FOLDED_STORE}, + {X86::VEXTRACTI32X4Zrri, X86::VEXTRACTI32X4Zmri, TB_FOLDED_STORE}, + {X86::VEXTRACTI32X8Zrri, X86::VEXTRACTI32X8Zmri, TB_FOLDED_STORE}, + {X86::VEXTRACTI64X2Z256rri, X86::VEXTRACTI64X2Z256mri, TB_FOLDED_STORE}, + {X86::VEXTRACTI64X2Zrri, X86::VEXTRACTI64X2Zmri, TB_FOLDED_STORE}, + {X86::VEXTRACTI64X4Zrri, X86::VEXTRACTI64X4Zmri, TB_FOLDED_STORE}, {X86::VEXTRACTPSZrri, X86::VEXTRACTPSZmri, TB_FOLDED_STORE}, {X86::VEXTRACTPSrri, X86::VEXTRACTPSmri, TB_FOLDED_STORE}, {X86::VMOV64toSDZrr, X86::MOV64mr, TB_FOLDED_STORE|TB_NO_REVERSE}, @@ -2998,19 +2998,19 @@ static const X86FoldTableEntry Table2[] = { {X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0}, {X86::VHSUBPSrr, X86::VHSUBPSrm, 0}, {X86::VINSERTF128rri, X86::VINSERTF128rmi, 0}, - {X86::VINSERTF32x4Z256rri, X86::VINSERTF32x4Z256rmi, 0}, - {X86::VINSERTF32x4Zrri, X86::VINSERTF32x4Zrmi, 0}, - {X86::VINSERTF32x8Zrri, X86::VINSERTF32x8Zrmi, 0}, - {X86::VINSERTF64x2Z256rri, X86::VINSERTF64x2Z256rmi, 0}, - {X86::VINSERTF64x2Zrri, X86::VINSERTF64x2Zrmi, 0}, - {X86::VINSERTF64x4Zrri, X86::VINSERTF64x4Zrmi, 0}, + {X86::VINSERTF32X4Z256rri, X86::VINSERTF32X4Z256rmi, 0}, + {X86::VINSERTF32X4Zrri, X86::VINSERTF32X4Zrmi, 0}, + {X86::VINSERTF32X8Zrri, X86::VINSERTF32X8Zrmi, 0}, + {X86::VINSERTF64X2Z256rri, X86::VINSERTF64X2Z256rmi, 0}, + {X86::VINSERTF64X2Zrri, X86::VINSERTF64X2Zrmi, 0}, + {X86::VINSERTF64X4Zrri, X86::VINSERTF64X4Zrmi, 0}, {X86::VINSERTI128rri, X86::VINSERTI128rmi, 0}, - {X86::VINSERTI32x4Z256rri, X86::VINSERTI32x4Z256rmi, 0}, - {X86::VINSERTI32x4Zrri, X86::VINSERTI32x4Zrmi, 0}, - {X86::VINSERTI32x8Zrri, X86::VINSERTI32x8Zrmi, 0}, - {X86::VINSERTI64x2Z256rri, X86::VINSERTI64x2Z256rmi, 0}, - {X86::VINSERTI64x2Zrri, X86::VINSERTI64x2Zrmi, 0}, - {X86::VINSERTI64x4Zrri, X86::VINSERTI64x4Zrmi, 0}, + {X86::VINSERTI32X4Z256rri, X86::VINSERTI32X4Z256rmi, 0}, + {X86::VINSERTI32X4Zrri, X86::VINSERTI32X4Zrmi, 0}, + {X86::VINSERTI32X8Zrri, X86::VINSERTI32X8Zrmi, 0}, + {X86::VINSERTI64X2Z256rri, X86::VINSERTI64X2Z256rmi, 0}, + {X86::VINSERTI64X2Zrri, X86::VINSERTI64X2Zrmi, 0}, + {X86::VINSERTI64X4Zrri, X86::VINSERTI64X4Zrmi, 0}, {X86::VMAXCPDYrr, X86::VMAXCPDYrm, 0}, {X86::VMAXCPDZ128rr, X86::VMAXCPDZ128rm, 0}, {X86::VMAXCPDZ256rr, X86::VMAXCPDZ256rm, 0}, @@ -5074,18 +5074,18 @@ static const X86FoldTableEntry Table3[] = { {X86::VGF2P8MULBZ128rrkz, X86::VGF2P8MULBZ128rmkz, 0}, {X86::VGF2P8MULBZ256rrkz, X86::VGF2P8MULBZ256rmkz, 0}, {X86::VGF2P8MULBZrrkz, X86::VGF2P8MULBZrmkz, 0}, - {X86::VINSERTF32x4Z256rrikz, X86::VINSERTF32x4Z256rmikz, 0}, - {X86::VINSERTF32x4Zrrikz, X86::VINSERTF32x4Zrmikz, 0}, - {X86::VINSERTF32x8Zrrikz, X86::VINSERTF32x8Zrmikz, 0}, - {X86::VINSERTF64x2Z256rrikz, X86::VINSERTF64x2Z256rmikz, 0}, - {X86::VINSERTF64x2Zrrikz, X86::VINSERTF64x2Zrmikz, 0}, - {X86::VINSERTF64x4Zrrikz, X86::VINSERTF64x4Zrmikz, 0}, - {X86::VINSERTI32x4Z256rrikz, X86::VINSERTI32x4Z256rmikz, 0}, - {X86::VINSERTI32x4Zrrikz, X86::VINSERTI32x4Zrmikz, 0}, - {X86::VINSERTI32x8Zrrikz, X86::VINSERTI32x8Zrmikz, 0}, - {X86::VINSERTI64x2Z256rrikz, X86::VINSERTI64x2Z256rmikz, 0}, - {X86::VINSERTI64x2Zrrikz, X86::VINSERTI64x2Zrmikz, 0}, - {X86::VINSERTI64x4Zrrikz, X86::VINSERTI64x4Zrmikz, 0}, + {X86::VINSERTF32X4Z256rrikz, X86::VINSERTF32X4Z256rmikz, 0}, + {X86::VINSERTF32X4Zrrikz, X86::VINSERTF32X4Zrmikz, 0}, + {X86::VINSERTF32X8Zrrikz, X86::VINSERTF32X8Zrmikz, 0}, + {X86::VINSERTF64X2Z256rrikz, X86::VINSERTF64X2Z256rmikz, 0}, + {X86::VINSERTF64X2Zrrikz, X86::VINSERTF64X2Zrmikz, 0}, + {X86::VINSERTF64X4Zrrikz, X86::VINSERTF64X4Zrmikz, 0}, + {X86::VINSERTI32X4Z256rrikz, X86::VINSERTI32X4Z256rmikz, 0}, + {X86::VINSERTI32X4Zrrikz, X86::VINSERTI32X4Zrmikz, 0}, + {X86::VINSERTI32X8Zrrikz, X86::VINSERTI32X8Zrmikz, 0}, + {X86::VINSERTI64X2Z256rrikz, X86::VINSERTI64X2Z256rmikz, 0}, + {X86::VINSERTI64X2Zrrikz, X86::VINSERTI64X2Zrmikz, 0}, + {X86::VINSERTI64X4Zrrikz, X86::VINSERTI64X4Zrmikz, 0}, {X86::VMAXCPDZ128rrkz, X86::VMAXCPDZ128rmkz, 0}, {X86::VMAXCPDZ256rrkz, X86::VMAXCPDZ256rmkz, 0}, {X86::VMAXCPDZrrkz, X86::VMAXCPDZrmkz, 0}, @@ -6696,18 +6696,18 @@ static const X86FoldTableEntry Table4[] = { {X86::VGF2P8MULBZ128rrk, X86::VGF2P8MULBZ128rmk, 0}, {X86::VGF2P8MULBZ256rrk, X86::VGF2P8MULBZ256rmk, 0}, {X86::VGF2P8MULBZrrk, X86::VGF2P8MULBZrmk, 0}, - {X86::VINSERTF32x4Z256rrik, X86::VINSERTF32x4Z256rmik, 0}, - {X86::VINSERTF32x4Zrrik, X86::VINSERTF32x4Zrmik, 0}, - {X86::VINSERTF32x8Zrrik, X86::VINSERTF32x8Zrmik, 0}, - {X86::VINSERTF64x2Z256rrik, X86::VINSERTF64x2Z256rmik, 0}, - {X86::VINSERTF64x2Zrrik, X86::VINSERTF64x2Zrmik, 0}, - {X86::VINSERTF64x4Zrrik, X86::VINSERTF64x4Zrmik, 0}, - {X86::VINSERTI32x4Z256rrik, X86::VINSERTI32x4Z256rmik, 0}, - {X86::VINSERTI32x4Zrrik, X86::VINSERTI32x4Zrmik, 0}, - {X86::VINSERTI32x8Zrrik, X86::VINSERTI32x8Zrmik, 0}, - {X86::VINSERTI64x2Z256rrik, X86::VINSERTI64x2Z256rmik, 0}, - {X86::VINSERTI64x2Zrrik, X86::VINSERTI64x2Zrmik, 0}, - {X86::VINSERTI64x4Zrrik, X86::VINSERTI64x4Zrmik, 0}, + {X86::VINSERTF32X4Z256rrik, X86::VINSERTF32X4Z256rmik, 0}, + {X86::VINSERTF32X4Zrrik, X86::VINSERTF32X4Zrmik, 0}, + {X86::VINSERTF32X8Zrrik, X86::VINSERTF32X8Zrmik, 0}, + {X86::VINSERTF64X2Z256rrik, X86::VINSERTF64X2Z256rmik, 0}, + {X86::VINSERTF64X2Zrrik, X86::VINSERTF64X2Zrmik, 0}, + {X86::VINSERTF64X4Zrrik, X86::VINSERTF64X4Zrmik, 0}, + {X86::VINSERTI32X4Z256rrik, X86::VINSERTI32X4Z256rmik, 0}, + {X86::VINSERTI32X4Zrrik, X86::VINSERTI32X4Zrmik, 0}, + {X86::VINSERTI32X8Zrrik, X86::VINSERTI32X8Zrmik, 0}, + {X86::VINSERTI64X2Z256rrik, X86::VINSERTI64X2Z256rmik, 0}, + {X86::VINSERTI64X2Zrrik, X86::VINSERTI64X2Zrmik, 0}, + {X86::VINSERTI64X4Zrrik, X86::VINSERTI64X4Zrmik, 0}, {X86::VMAXCPDZ128rrk, X86::VMAXCPDZ128rmk, 0}, {X86::VMAXCPDZ256rrk, X86::VMAXCPDZ256rmk, 0}, {X86::VMAXCPDZrrk, X86::VMAXCPDZrmk, 0}, diff --git a/llvm/test/TableGen/x86-instr-mapping.inc b/llvm/test/TableGen/x86-instr-mapping.inc index 256686612c6a2..b972427c2ff7a 100644 --- a/llvm/test/TableGen/x86-instr-mapping.inc +++ b/llvm/test/TableGen/x86-instr-mapping.inc @@ -360,14 +360,14 @@ static const X86TableEntry X86CompressEVEXTable[] = { { X86::VDIVSSZrm_Int, X86::VDIVSSrm_Int }, { X86::VDIVSSZrr, X86::VDIVSSrr }, { X86::VDIVSSZrr_Int, X86::VDIVSSrr_Int }, - { X86::VEXTRACTF32x4Z256mri, X86::VEXTRACTF128mri }, - { X86::VEXTRACTF32x4Z256rri, X86::VEXTRACTF128rri }, - { X86::VEXTRACTF64x2Z256mri, X86::VEXTRACTF128mri }, - { X86::VEXTRACTF64x2Z256rri, X86::VEXTRACTF128rri }, - { X86::VEXTRACTI32x4Z256mri, X86::VEXTRACTI128mri }, - { X86::VEXTRACTI32x4Z256rri, X86::VEXTRACTI128rri }, - { X86::VEXTRACTI64x2Z256mri, X86::VEXTRACTI128mri }, - { X86::VEXTRACTI64x2Z256rri, X86::VEXTRACTI128rri }, + { X86::VEXTRACTF32X4Z256mri, X86::VEXTRACTF128mri }, + { X86::VEXTRACTF32X4Z256rri, X86::VEXTRACTF128rri }, + { X86::VEXTRACTF64X2Z256mri, X86::VEXTRACTF128mri }, + { X86::VEXTRACTF64X2Z256rri, X86::VEXTRACTF128rri }, + { X86::VEXTRACTI32X4Z256mri, X86::VEXTRACTI128mri }, + { X86::VEXTRACTI32X4Z256rri, X86::VEXTRACTI128rri }, + { X86::VEXTRACTI64X2Z256mri, X86::VEXTRACTI128mri }, + { X86::VEXTRACTI64X2Z256rri, X86::VEXTRACTI128rri }, { X86::VEXTRACTPSZmri, X86::VEXTRACTPSmri }, { X86::VEXTRACTPSZrri, X86::VEXTRACTPSrri }, { X86::VFMADD132PDZ128m, X86::VFMADD132PDm }, @@ -622,14 +622,14 @@ static const X86TableEntry X86CompressEVEXTable[] = { { X86::VGF2P8MULBZ128rr, X86::VGF2P8MULBrr }, { X86::VGF2P8MULBZ256rm, X86::VGF2P8MULBYrm }, { X86::VGF2P8MULBZ256rr, X86::VGF2P8MULBYrr }, - { X86::VINSERTF32x4Z256rmi, X86::VINSERTF128rmi }, - { X86::VINSERTF32x4Z256rri, X86::VINSERTF128rri }, - { X86::VINSERTF64x2Z256rmi, X86::VINSERTF128rmi }, - { X86::VINSERTF64x2Z256rri, X86::VINSERTF128rri }, - { X86::VINSERTI32x4Z256rmi, X86::VINSERTI128rmi }, - { X86::VINSERTI32x4Z256rri, X86::VINSERTI128rri }, - { X86::VINSERTI64x2Z256rmi, X86::VINSERTI128rmi }, - { X86::VINSERTI64x2Z256rri, X86::VINSERTI128rri }, + { X86::VINSERTF32X4Z256rmi, X86::VINSERTF128rmi }, + { X86::VINSERTF32X4Z256rri, X86::VINSERTF128rri }, + { X86::VINSERTF64X2Z256rmi, X86::VINSERTF128rmi }, + { X86::VINSERTF64X2Z256rri, X86::VINSERTF128rri }, + { X86::VINSERTI32X4Z256rmi, X86::VINSERTI128rmi }, + { X86::VINSERTI32X4Z256rri, X86::VINSERTI128rri }, + { X86::VINSERTI64X2Z256rmi, X86::VINSERTI128rmi }, + { X86::VINSERTI64X2Z256rri, X86::VINSERTI128rri }, { X86::VINSERTPSZrmi, X86::VINSERTPSrmi }, { X86::VINSERTPSZrri, X86::VINSERTPSrri }, { X86::VMAXCPDZ128rm, X86::VMAXCPDrm }, diff --git a/llvm/utils/TableGen/X86ManualFoldTables.def b/llvm/utils/TableGen/X86ManualFoldTables.def index 4a58deaa0ff1b..003712ae124c7 100644 --- a/llvm/utils/TableGen/X86ManualFoldTables.def +++ b/llvm/utils/TableGen/X86ManualFoldTables.def @@ -31,18 +31,18 @@ NOFOLD(VCOMPRESSPSZrrk) NOFOLD(VCVTPS2PHZ128rrk) NOFOLD(VCVTPS2PHZ256rrk) NOFOLD(VCVTPS2PHZrrk) -NOFOLD(VEXTRACTF32x4Z256rrik) -NOFOLD(VEXTRACTF32x4Zrrik) -NOFOLD(VEXTRACTF32x8Zrrik) -NOFOLD(VEXTRACTF64x2Z256rrik) -NOFOLD(VEXTRACTF64x2Zrrik) -NOFOLD(VEXTRACTF64x4Zrrik) -NOFOLD(VEXTRACTI32x4Z256rrik) -NOFOLD(VEXTRACTI32x4Zrrik) -NOFOLD(VEXTRACTI32x8Zrrik) -NOFOLD(VEXTRACTI64x2Z256rrik) -NOFOLD(VEXTRACTI64x2Zrrik) -NOFOLD(VEXTRACTI64x4Zrrik) +NOFOLD(VEXTRACTF32X4Z256rrik) +NOFOLD(VEXTRACTF32X4Zrrik) +NOFOLD(VEXTRACTF32X8Zrrik) +NOFOLD(VEXTRACTF64X2Z256rrik) +NOFOLD(VEXTRACTF64X2Zrrik) +NOFOLD(VEXTRACTF64X4Zrrik) +NOFOLD(VEXTRACTI32X4Z256rrik) +NOFOLD(VEXTRACTI32X4Zrrik) +NOFOLD(VEXTRACTI32X8Zrrik) +NOFOLD(VEXTRACTI64X2Z256rrik) +NOFOLD(VEXTRACTI64X2Zrrik) +NOFOLD(VEXTRACTI64X4Zrrik) NOFOLD(VMOVAPDZ128mrk) NOFOLD(VMOVAPDZ256mrk) NOFOLD(VMOVAPDZmrk) diff --git a/llvm/utils/TableGen/X86ManualInstrMapping.def b/llvm/utils/TableGen/X86ManualInstrMapping.def index 7c5a6033237fe..2fdc4dc90f340 100644 --- a/llvm/utils/TableGen/X86ManualInstrMapping.def +++ b/llvm/utils/TableGen/X86ManualInstrMapping.def @@ -246,14 +246,14 @@ ENTRY(VCVTTPD2DQZ256rm, VCVTTPD2DQYrm) ENTRY(VCVTTPD2DQZ256rr, VCVTTPD2DQYrr) ENTRY(VDIVPDZ256rm, VDIVPDYrm) ENTRY(VDIVPDZ256rr, VDIVPDYrr) -ENTRY(VEXTRACTF64x2Z256mri, VEXTRACTF128mri) -ENTRY(VEXTRACTF64x2Z256rri, VEXTRACTF128rri) -ENTRY(VEXTRACTI64x2Z256mri, VEXTRACTI128mri) -ENTRY(VEXTRACTI64x2Z256rri, VEXTRACTI128rri) -ENTRY(VINSERTF64x2Z256rmi, VINSERTF128rmi) -ENTRY(VINSERTF64x2Z256rri, VINSERTF128rri) -ENTRY(VINSERTI64x2Z256rmi, VINSERTI128rmi) -ENTRY(VINSERTI64x2Z256rri, VINSERTI128rri) +ENTRY(VEXTRACTF64X2Z256mri, VEXTRACTF128mri) +ENTRY(VEXTRACTF64X2Z256rri, VEXTRACTF128rri) +ENTRY(VEXTRACTI64X2Z256mri, VEXTRACTI128mri) +ENTRY(VEXTRACTI64X2Z256rri, VEXTRACTI128rri) +ENTRY(VINSERTF64X2Z256rmi, VINSERTF128rmi) +ENTRY(VINSERTF64X2Z256rri, VINSERTF128rri) +ENTRY(VINSERTI64X2Z256rmi, VINSERTI128rmi) +ENTRY(VINSERTI64X2Z256rri, VINSERTI128rri) ENTRY(VMAXCPDZ256rm, VMAXCPDYrm) ENTRY(VMAXCPDZ256rr, VMAXCPDYrr) ENTRY(VMAXPDZ256rm, VMAXPDYrm) From ac3fda613119c3a391b5acc26040cfd6352d3563 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 19 Nov 2024 16:54:05 +0000 Subject: [PATCH 2/2] Fix GISel tests --- .../X86/GlobalISel/select-extract-vec256.mir | 2 +- .../X86/GlobalISel/select-extract-vec512.mir | 4 ++-- .../X86/GlobalISel/select-insert-vec256.mir | 6 ++--- .../X86/GlobalISel/select-insert-vec512.mir | 24 +++++++++---------- .../X86/GlobalISel/select-merge-vec256.mir | 4 ++-- .../X86/GlobalISel/select-merge-vec512.mir | 12 +++++----- .../X86/GlobalISel/select-unmerge-vec256.mir | 4 ++-- .../X86/GlobalISel/select-unmerge-vec512.mir | 8 +++---- 8 files changed, 32 insertions(+), 32 deletions(-) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir index 301d63b7f3643..fda9f8a010f3d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir @@ -65,7 +65,7 @@ registers: # AVX-NEXT: RET 0, implicit $xmm0 # # AVX512VL: %0:vr256x = COPY $ymm1 -# AVX512VL-NEXT: %1:vr128x = VEXTRACTF32x4Z256rri %0, 1 +# AVX512VL-NEXT: %1:vr128x = VEXTRACTF32X4Z256rri %0, 1 # AVX512VL-NEXT: $xmm0 = COPY %1 # AVX512VL-NEXT: RET 0, implicit $xmm0 body: | diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir index cff8560a4ba45..3f199448e89a6 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir @@ -59,7 +59,7 @@ registers: - { id: 0, class: vecr } - { id: 1, class: vecr } # ALL: %0:vr512 = COPY $zmm1 -# ALL-NEXT: %1:vr128x = VEXTRACTF32x4Zrri %0, 1 +# ALL-NEXT: %1:vr128x = VEXTRACTF32X4Zrri %0, 1 # ALL-NEXT: $xmm0 = COPY %1 # ALL-NEXT: RET 0, implicit $xmm0 body: | @@ -111,7 +111,7 @@ registers: - { id: 0, class: vecr } - { id: 1, class: vecr } # ALL: %0:vr512 = COPY $zmm1 -# ALL-NEXT: %1:vr256x = VEXTRACTF64x4Zrri %0, 1 +# ALL-NEXT: %1:vr256x = VEXTRACTF64X4Zrri %0, 1 # ALL-NEXT: $ymm0 = COPY %1 # ALL-NEXT: RET 0, implicit $ymm0 body: | diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir index f04917c747979..3368ed699a1f8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir @@ -36,7 +36,7 @@ registers: # # AVX512VL: %0:vr256x = COPY $ymm0 # AVX512VL-NEXT: %1:vr128x = COPY $xmm1 -# AVX512VL-NEXT: %2:vr256x = VINSERTF32x4Z256rri %0, %1, 0 +# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 0 # AVX512VL-NEXT: $ymm0 = COPY %2 # AVX512VL-NEXT: RET 0, implicit $ymm0 body: | @@ -98,7 +98,7 @@ registers: # # AVX512VL: %0:vr256x = COPY $ymm0 # AVX512VL-NEXT: %1:vr128x = COPY $xmm1 -# AVX512VL-NEXT: %2:vr256x = VINSERTF32x4Z256rri %0, %1, 1 +# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 1 # AVX512VL-NEXT: $ymm0 = COPY %2 # AVX512VL-NEXT: RET 0, implicit $ymm0 body: | @@ -129,7 +129,7 @@ registers: # # AVX512VL: %0:vr256x = IMPLICIT_DEF # AVX512VL-NEXT: %1:vr128x = COPY $xmm1 -# AVX512VL-NEXT: %2:vr256x = VINSERTF32x4Z256rri %0, %1, 1 +# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 1 # AVX512VL-NEXT: $ymm0 = COPY %2 # AVX512VL-NEXT: RET 0, implicit $ymm0 body: | diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir index 10d98d7a3111b..6fb59df0736da 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir @@ -51,8 +51,8 @@ body: | ; ALL-LABEL: name: test_insert_128_idx0 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1 - ; ALL: [[VINSERTF32x4Zrri:%[0-9]+]]:vr512 = VINSERTF32x4Zrri [[COPY]], [[COPY1]], 0 - ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrri]] + ; ALL: [[VINSERTF32X4Zrri:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[COPY]], [[COPY1]], 0 + ; ALL: $zmm0 = COPY [[VINSERTF32X4Zrri]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = COPY $zmm0 %1(<4 x s32>) = COPY $xmm1 @@ -102,8 +102,8 @@ body: | ; ALL-LABEL: name: test_insert_128_idx1 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1 - ; ALL: [[VINSERTF32x4Zrri:%[0-9]+]]:vr512 = VINSERTF32x4Zrri [[COPY]], [[COPY1]], 1 - ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrri]] + ; ALL: [[VINSERTF32X4Zrri:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[COPY]], [[COPY1]], 1 + ; ALL: $zmm0 = COPY [[VINSERTF32X4Zrri]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = COPY $zmm0 %1(<4 x s32>) = COPY $xmm1 @@ -127,8 +127,8 @@ body: | ; ALL-LABEL: name: test_insert_128_idx1_undef ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1 - ; ALL: [[VINSERTF32x4Zrri:%[0-9]+]]:vr512 = VINSERTF32x4Zrri [[DEF]], [[COPY]], 1 - ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrri]] + ; ALL: [[VINSERTF32X4Zrri:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[DEF]], [[COPY]], 1 + ; ALL: $zmm0 = COPY [[VINSERTF32X4Zrri]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = IMPLICIT_DEF %1(<4 x s32>) = COPY $xmm1 @@ -152,8 +152,8 @@ body: | ; ALL-LABEL: name: test_insert_256_idx0 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1 - ; ALL: [[VINSERTF64x4Zrri:%[0-9]+]]:vr512 = VINSERTF64x4Zrri [[COPY]], [[COPY1]], 0 - ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrri]] + ; ALL: [[VINSERTF64X4Zrri:%[0-9]+]]:vr512 = VINSERTF64X4Zrri [[COPY]], [[COPY1]], 0 + ; ALL: $zmm0 = COPY [[VINSERTF64X4Zrri]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = COPY $zmm0 %1(<8 x s32>) = COPY $ymm1 @@ -203,8 +203,8 @@ body: | ; ALL-LABEL: name: test_insert_256_idx1 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1 - ; ALL: [[VINSERTF64x4Zrri:%[0-9]+]]:vr512 = VINSERTF64x4Zrri [[COPY]], [[COPY1]], 1 - ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrri]] + ; ALL: [[VINSERTF64X4Zrri:%[0-9]+]]:vr512 = VINSERTF64X4Zrri [[COPY]], [[COPY1]], 1 + ; ALL: $zmm0 = COPY [[VINSERTF64X4Zrri]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = COPY $zmm0 %1(<8 x s32>) = COPY $ymm1 @@ -228,8 +228,8 @@ body: | ; ALL-LABEL: name: test_insert_256_idx1_undef ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY $ymm1 - ; ALL: [[VINSERTF64x4Zrri:%[0-9]+]]:vr512 = VINSERTF64x4Zrri [[DEF]], [[COPY]], 1 - ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrri]] + ; ALL: [[VINSERTF64X4Zrri:%[0-9]+]]:vr512 = VINSERTF64X4Zrri [[DEF]], [[COPY]], 1 + ; ALL: $zmm0 = COPY [[VINSERTF64X4Zrri]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = IMPLICIT_DEF %1(<8 x s32>) = COPY $ymm1 diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir index 9d6494d628bf0..83ce6eb0b17be 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir @@ -29,8 +29,8 @@ body: | ; AVX512VL-LABEL: name: test_merge ; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF ; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]] - ; AVX512VL: [[VINSERTF32x4Z256rri:%[0-9]+]]:vr256x = VINSERTF32x4Z256rri %2, [[DEF]], 1 - ; AVX512VL: $ymm0 = COPY [[VINSERTF32x4Z256rri]] + ; AVX512VL: [[VINSERTF32X4Z256rri:%[0-9]+]]:vr256x = VINSERTF32X4Z256rri %2, [[DEF]], 1 + ; AVX512VL: $ymm0 = COPY [[VINSERTF32X4Z256rri]] ; AVX512VL: RET 0, implicit $ymm0 %0(<4 x s32>) = IMPLICIT_DEF %1(<8 x s32>) = G_CONCAT_VECTORS %0(<4 x s32>), %0(<4 x s32>) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir index 22045d3bb8cbb..d8e3c3aea262b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir @@ -24,10 +24,10 @@ body: | ; ALL-LABEL: name: test_merge_v128 ; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF ; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]] - ; ALL: [[VINSERTF32x4Zrri:%[0-9]+]]:vr512 = VINSERTF32x4Zrri %2, [[DEF]], 1 - ; ALL: [[VINSERTF32x4Zrri1:%[0-9]+]]:vr512 = VINSERTF32x4Zrri [[VINSERTF32x4Zrri]], [[DEF]], 2 - ; ALL: [[VINSERTF32x4Zrri2:%[0-9]+]]:vr512 = VINSERTF32x4Zrri [[VINSERTF32x4Zrri1]], [[DEF]], 3 - ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrri2]] + ; ALL: [[VINSERTF32X4Zrri:%[0-9]+]]:vr512 = VINSERTF32X4Zrri %2, [[DEF]], 1 + ; ALL: [[VINSERTF32X4Zrri1:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[VINSERTF32X4Zrri]], [[DEF]], 2 + ; ALL: [[VINSERTF32X4Zrri2:%[0-9]+]]:vr512 = VINSERTF32X4Zrri [[VINSERTF32X4Zrri1]], [[DEF]], 3 + ; ALL: $zmm0 = COPY [[VINSERTF32X4Zrri2]] ; ALL: RET 0, implicit $zmm0 %0(<4 x s32>) = IMPLICIT_DEF %1(<16 x s32>) = G_CONCAT_VECTORS %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>) @@ -49,8 +49,8 @@ body: | ; ALL-LABEL: name: test_merge_v256 ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]] - ; ALL: [[VINSERTF64x4Zrri:%[0-9]+]]:vr512 = VINSERTF64x4Zrri %2, [[DEF]], 1 - ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrri]] + ; ALL: [[VINSERTF64X4Zrri:%[0-9]+]]:vr512 = VINSERTF64X4Zrri %2, [[DEF]], 1 + ; ALL: $zmm0 = COPY [[VINSERTF64X4Zrri]] ; ALL: RET 0, implicit $zmm0 %0(<8 x s32>) = IMPLICIT_DEF %1(<16 x s32>) = G_CONCAT_VECTORS %0(<8 x s32>), %0(<8 x s32>) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir index 5ed1463f873a9..920d66c3fc0b3 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir @@ -33,9 +33,9 @@ body: | ; AVX512VL-LABEL: name: test_unmerge ; AVX512VL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm - ; AVX512VL-NEXT: [[VEXTRACTF32x4Z256rri:%[0-9]+]]:vr128x = VEXTRACTF32x4Z256rri [[DEF]], 1 + ; AVX512VL-NEXT: [[VEXTRACTF32X4Z256rri:%[0-9]+]]:vr128x = VEXTRACTF32X4Z256rri [[DEF]], 1 ; AVX512VL-NEXT: $xmm0 = COPY [[COPY]] - ; AVX512VL-NEXT: $xmm1 = COPY [[VEXTRACTF32x4Z256rri]] + ; AVX512VL-NEXT: $xmm1 = COPY [[VEXTRACTF32X4Z256rri]] ; AVX512VL-NEXT: RET 0, implicit $xmm0, implicit $xmm1 %0(<8 x s32>) = IMPLICIT_DEF %1(<4 x s32>), %2(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir index 8864d5bb47488..785cf79ca1db9 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir @@ -27,9 +27,9 @@ body: | ; ALL-LABEL: name: test_unmerge_v128 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm - ; ALL: [[VEXTRACTF32x4Zrri:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrri [[DEF]], 1 - ; ALL: [[VEXTRACTF32x4Zrri1:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrri [[DEF]], 2 - ; ALL: [[VEXTRACTF32x4Zrri2:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrri [[DEF]], 3 + ; ALL: [[VEXTRACTF32X4Zrri:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 1 + ; ALL: [[VEXTRACTF32X4Zrri1:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 2 + ; ALL: [[VEXTRACTF32X4Zrri2:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 3 ; ALL: $xmm0 = COPY [[COPY]] ; ALL: RET 0, implicit $xmm0 %0(<16 x s32>) = IMPLICIT_DEF @@ -53,7 +53,7 @@ body: | ; ALL-LABEL: name: test_unmerge_v256 ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY [[DEF]].sub_ymm - ; ALL: [[VEXTRACTF64x4Zrri:%[0-9]+]]:vr256x = VEXTRACTF64x4Zrri [[DEF]], 1 + ; ALL: [[VEXTRACTF64X4Zrri:%[0-9]+]]:vr256x = VEXTRACTF64X4Zrri [[DEF]], 1 ; ALL: $ymm0 = COPY [[COPY]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = IMPLICIT_DEF