From 363c2f3734db60448ccc4be27a43169ce2f3ab53 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 28 Nov 2024 13:12:14 +0800 Subject: [PATCH] [RISCV] Rename some Feature* to Tune* These features should be tune features. --- llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++-- llvm/lib/Target/RISCV/RISCVProcessors.td | 22 +++++++++---------- ...ert-highly-predictable-select-to-branch.ll | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 7f0bdf362357c..3fb76c77e32fd 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1388,10 +1388,10 @@ def FeatureUnalignedVectorMem "true", "Has reasonably performant unaligned vector " "loads and stores">; -def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", +def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; -def FeaturePredictableSelectIsExpensive +def TunePredictableSelectIsExpensive : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true", "Prefer likely predicted branches over selects">; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 145af4ea80f6d..471f051728e99 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -95,7 +95,7 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll, TuneShortForwardBranchOpt, - FeaturePostRAScheduler]; + TunePostRAScheduler]; def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series", SiFive7Model, SiFive7TuneFeatures>; @@ -251,7 +251,7 @@ defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll, TuneConditionalCompressedMoveFusion, TuneLUIADDIFusion, TuneAUIPCADDIFusion, - FeaturePostRAScheduler]; + TunePostRAScheduler]; def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, !listconcat(RVA22U64Features, @@ -300,7 +300,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneAUIPCADDIFusion, TuneNoSinkSplatOperands, TuneVXRMPipelineFlush, - FeaturePostRAScheduler]>; + TunePostRAScheduler]>; def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model, @@ -329,7 +329,7 @@ def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32", FeatureStdExtZifencei, FeatureStdExtM, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", SyntacoreSCR3RV64Model, @@ -340,7 +340,7 @@ def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", FeatureStdExtM, FeatureStdExtA, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32", SyntacoreSCR4RV32Model, @@ -352,7 +352,7 @@ def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64", SyntacoreSCR4RV64Model, @@ -365,7 +365,7 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32", SyntacoreSCR5RV32Model, @@ -378,7 +378,7 @@ def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64", SyntacoreSCR5RV64Model, @@ -391,7 +391,7 @@ def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", SyntacoreSCR7Model, @@ -410,7 +410,7 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZbc, FeatureStdExtZbs, FeatureStdExtZkn], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", NoSchedModel, @@ -432,7 +432,7 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", FeatureUnalignedVectorMem]), [TuneNoDefaultUnroll, TuneOptimizedZeroStrideLoad, - FeaturePostRAScheduler]>; + TunePostRAScheduler]>; def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", NoSchedModel, diff --git a/llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll b/llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll index 1abd774d7a487..87c666399e03c 100644 --- a/llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll +++ b/llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll @@ -19,7 +19,7 @@ entry: } ; Test has highly predictable select according to profile data, -; which should be transformed to a branch on cores with enabled FeaturePredictableSelectIsExpensive +; which should be transformed to a branch on cores with enabled TunePredictableSelectIsExpensive define i32 @test2(i32 %a) { ; CHEAP-LABEL: test2: ; CHEAP: # %bb.0: # %entry