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[X86] Lower CTTZ/CTLZ vXi8 vectors using GF2P8AFFINEQB #118012

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[X86] Lower CTTZ/CTLZ vXi8 vectors using GF2P8AFFINEQB #118012

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28 changes: 28 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1330,6 +1330,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::BITREVERSE, MVT::i16, Custom);
setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
setOperationAction(ISD::BITREVERSE, MVT::i64, Custom);
setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
}

if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
Expand Down Expand Up @@ -1695,6 +1697,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
setOperationAction(ISD::MGATHER, VT, Custom);
}

if (Subtarget.hasGFNI()) {
setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
}
}

if (!Subtarget.useSoftFloat() && !Subtarget.hasFP16() &&
Expand Down Expand Up @@ -2079,6 +2086,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FNEG, MVT::v32f16, Custom);
setOperationAction(ISD::FABS, MVT::v32f16, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::v32f16, Custom);

if (Subtarget.hasGFNI()) {
setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
setOperationAction(ISD::CTTZ, MVT::v64i8, Custom);
}
}// useAVX512Regs

if (!Subtarget.useSoftFloat() && Subtarget.hasVBMI2()) {
Expand Down Expand Up @@ -28418,6 +28430,9 @@ uint64_t getGFNICtrlImm(unsigned Opcode, unsigned Amt = 0) {
switch (Opcode) {
case ISD::BITREVERSE:
return 0x8040201008040201ULL;
case ISD::CTTZ:
// Special case - only works for zero/single bit input.
return 0xAACCF0FF00000000ULL;
case ISD::SHL:
return ((0x0102040810204080ULL >> (Amt)) &
(0x0101010101010101ULL * (0xFF >> (Amt))));
Expand Down Expand Up @@ -28572,6 +28587,11 @@ static SDValue LowerVectorCTLZ(SDValue Op, const SDLoc &DL,
SelectionDAG &DAG) {
MVT VT = Op.getSimpleValueType();

// GFNI targets - fold as cttz(bitreverse())
if (Subtarget.hasGFNI() && VT.getVectorElementType() == MVT::i8)
return DAG.getNode(ISD::CTTZ, DL, VT,
DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(0)));

if (Subtarget.hasCDI() &&
// vXi8 vectors need to be promoted to 512-bits for vXi32.
(Subtarget.canExtendTo512DQ() || VT.getVectorElementType() != MVT::i8))
Expand Down Expand Up @@ -28635,6 +28655,14 @@ static SDValue LowerCTTZ(SDValue Op, const X86Subtarget &Subtarget,
SDValue N0 = Op.getOperand(0);
SDLoc dl(Op);

// GFNI - isolate LSB and perform GF2P8AFFINEQB lookup.
if (Subtarget.hasGFNI() && VT.isVector()) {
SDValue B = DAG.getNode(ISD::AND, dl, VT, N0, DAG.getNegative(N0, dl, VT));
SDValue M = getGFNICtrlMask(ISD::CTTZ, DAG, dl, VT);
return DAG.getNode(X86ISD::GF2P8AFFINEQB, dl, VT, B, M,
DAG.getTargetConstant(0x8, dl, MVT::i8));
}

assert(!VT.isVector() && Op.getOpcode() == ISD::CTTZ &&
"Only scalar CTTZ requires custom lowering");

Expand Down
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