From c5ea768bd956e1c048b27114c6a26f35fdd8b6c4 Mon Sep 17 00:00:00 2001 From: Luke Quinn Date: Mon, 2 Dec 2024 11:13:36 -0800 Subject: [PATCH] [RISCV] Add FPClass to Only Use FP for register bank selection Signed-off-by: Luke Quinn --- .../RISCV/GISel/RISCVRegisterBankInfo.cpp | 9 ++++++--- .../CodeGen/RISCV/GlobalISel/float-fclass.ll | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp index 829c0ac92c52a..a082b18867666 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp @@ -151,6 +151,7 @@ bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI, switch (MI.getOpcode()) { case RISCV::G_FCVT_W_RV64: case RISCV::G_FCVT_WU_RV64: + case RISCV::G_FCLASS: case TargetOpcode::G_FPTOSI: case TargetOpcode::G_FPTOUI: case TargetOpcode::G_FCMP: @@ -326,19 +327,21 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // Use FPR64 for s64 loads on rv32. if (GPRSize == 32 && Size.getFixedValue() == 64) { assert(MF.getSubtarget().hasStdExtD()); - OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits()); + OpdsMapping[0] = getFPValueMapping(Size); break; } // Check if that load feeds fp instructions. // In that case, we want the default mapping to be on FPR // instead of blind map every scalar to GPR. - if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI)) + if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI)) { // If we have at least one direct use in a FP instruction, // assume this was a floating point load in the IR. If it was // not, we would have had a bitcast before reaching that // instruction. - OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits()); + OpdsMapping[0] = getFPValueMapping(Size); + break; + } break; } diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll new file mode 100644 index 0000000000000..b846302c8a3c0 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll @@ -0,0 +1,19 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 + +; RUN: llc -mtriple=riscv32 -mattr=+f -global-isel \ +; RUN: < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -mattr=+f -global-isel \ +; RUN: < %s | FileCheck %s --check-prefixes=CHECK + +define i1 @fpclass(ptr %x) { +; CHECK-LABEL: fpclass: +; CHECK: # %bb.0: +; CHECK-NEXT: flw fa5, 0(a0) +; CHECK-NEXT: fclass.s a0, fa5 +; CHECK-NEXT: andi a0, a0, 927 +; CHECK-NEXT: snez a0, a0 +; CHECK-NEXT: ret + %a = load float, ptr %x + %cmp = call i1 @llvm.is.fpclass.f32(float %a, i32 639) + ret i1 %cmp +}