[OpenMP] Use generic IR for the OpenMP DeviceRTL #119091
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -44,7 +44,6 @@ void gpu_irregular_warp_reduce(void *reduce_data, ShuffleReductFnTy shflFct, | |
| } | ||
| } | ||
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| static uint32_t gpu_irregular_simd_reduce(void *reduce_data, | ||
| ShuffleReductFnTy shflFct) { | ||
| uint32_t size, remote_id, physical_lane_id; | ||
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@@ -63,7 +62,6 @@ static uint32_t gpu_irregular_simd_reduce(void *reduce_data, | |
| } while (logical_lane_id % 2 == 0 && size > 1); | ||
| return (logical_lane_id == 0); | ||
| } | ||
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| static int32_t nvptx_parallel_reduce_nowait(void *reduce_data, | ||
| ShuffleReductFnTy shflFct, | ||
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@@ -74,49 +72,53 @@ static int32_t nvptx_parallel_reduce_nowait(void *reduce_data, | |
| uint32_t NumThreads = omp_get_num_threads(); | ||
| if (NumThreads == 1) | ||
| return 1; | ||
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| // | ||
| // This reduce function handles reduction within a team. It handles | ||
| // parallel regions in both L1 and L2 parallelism levels. It also | ||
| // supports Generic, SPMD, and NoOMP modes. | ||
| // | ||
| // 1. Reduce within a warp. | ||
| // 2. Warp master copies value to warp 0 via shared memory. | ||
| // 3. Warp 0 reduces to a single value. | ||
| // 4. The reduced value is available in the thread that returns 1. | ||
| // | ||
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| #if __has_builtin(__nvvm_reflect) | ||
| if (__nvvm_reflect("__CUDA_ARCH") >= 700) { | ||
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Contributor
There was a problem hiding this comment. I'll try to make an AMDGPU counterpart for this one, though it doesn't look like necessary for the purpose of OpenMP device runtime.
Contributor
Author
There was a problem hiding this comment. I believe @AlexVlx also has interest in that space, so best consult with him as well. |
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| uint32_t WarpsNeeded = | ||
| (NumThreads + mapping::getWarpSize() - 1) / mapping::getWarpSize(); | ||
| uint32_t WarpId = mapping::getWarpIdInBlock(); | ||
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| // Volta execution model: | ||
| // For the Generic execution mode a parallel region either has 1 thread and | ||
| // beyond that, always a multiple of 32. For the SPMD execution mode we may | ||
| // have any number of threads. | ||
| if ((NumThreads % mapping::getWarpSize() == 0) || | ||
| (WarpId < WarpsNeeded - 1)) | ||
| gpu_regular_warp_reduce(reduce_data, shflFct); | ||
| else if (NumThreads > 1) // Only SPMD execution mode comes thru this case. | ||
| gpu_irregular_warp_reduce( | ||
| reduce_data, shflFct, | ||
| /*LaneCount=*/NumThreads % mapping::getWarpSize(), | ||
| /*LaneId=*/mapping::getThreadIdInBlock() % mapping::getWarpSize()); | ||
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| // When we have more than [mapping::getWarpSize()] number of threads | ||
| // a block reduction is performed here. | ||
| // | ||
| // Only L1 parallel region can enter this if condition. | ||
| if (NumThreads > mapping::getWarpSize()) { | ||
| // Gather all the reduced values from each warp | ||
| // to the first warp. | ||
| cpyFct(reduce_data, WarpsNeeded); | ||
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| if (WarpId == 0) | ||
| gpu_irregular_warp_reduce(reduce_data, shflFct, WarpsNeeded, | ||
| BlockThreadId); | ||
| } | ||
| return BlockThreadId == 0; | ||
| } | ||
| #endif | ||
| __kmpc_impl_lanemask_t Liveness = mapping::activemask(); | ||
| if (Liveness == lanes::All) // Full warp | ||
| gpu_regular_warp_reduce(reduce_data, shflFct); | ||
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@@ -150,10 +152,9 @@ static int32_t nvptx_parallel_reduce_nowait(void *reduce_data, | |
| return BlockThreadId == 0; | ||
| } | ||
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| // Get the OMP thread Id. This is different from BlockThreadId in the case | ||
| // of an L2 parallel region. | ||
| return BlockThreadId == 0; | ||
| } | ||
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| uint32_t roundToWarpsize(uint32_t s) { | ||
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and nothing after
-march=?There was a problem hiding this comment.
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Intentional
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so which means there is no arch?