From 1288e5f86a4045a7e49f9ba5675bed9e17ec9550 Mon Sep 17 00:00:00 2001 From: guochen2 Date: Mon, 9 Dec 2024 21:47:15 -0500 Subject: [PATCH] VOP2 test change for v_mul_f16 --- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 3 +- llvm/test/MC/AMDGPU/gfx11_asm_vop2.s | 75 ++++++++++-------- llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s | 65 +++++++++------- llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s | 21 +++-- llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s | 63 ++++++++++----- .../MC/AMDGPU/gfx11_asm_vop2_t16_promote.s | 63 ++++++++++----- .../AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s | 68 ++++++++++------- .../MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s | 28 +++++-- .../test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s | 69 +++++++++-------- llvm/test/MC/AMDGPU/gfx12_asm_vop2.s | 72 ++++++++++-------- llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s | 62 ++++++++------- llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s | 18 +++-- llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s | 63 ++++++++++----- .../MC/AMDGPU/gfx12_asm_vop2_t16_promote.s | 63 ++++++++++----- .../test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s | 69 +++++++++-------- .../AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s | 76 +++++++++++-------- .../MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s | 36 ++++++--- 17 files changed, 572 insertions(+), 342 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index 384fec0079a5d..355528a1f9295 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -1822,8 +1822,7 @@ defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">; defm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">; defm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">; -defm V_MUL_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">; -defm V_MUL_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">; +defm V_MUL_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x035, "v_mul_f16">; defm V_FMAC_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">; defm V_LDEXP_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">; defm V_LDEXP_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">; diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s index cb7b71935e22a..440c7201f541b 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s @@ -1582,50 +1582,65 @@ v_mul_dx9_zero_f32 v5, src_scc, v2 v_mul_dx9_zero_f32 v255, 0xaf123456, v255 // GFX11: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] -v_mul_f16 v5, v1, v2 -// GFX11: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6a] +v_mul_f16 v5.l, v1.l, v2.l +// GFX11: v_mul_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x6a] -v_mul_f16 v5, v127, v2 -// GFX11: v_mul_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6a] +v_mul_f16 v5.l, v127.l, v2.l +// GFX11: v_mul_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x6a] -v_mul_f16 v5, s1, v2 -// GFX11: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6a] +v_mul_f16 v5.l, s1, v2.l +// GFX11: v_mul_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x6a] -v_mul_f16 v5, s105, v2 -// GFX11: v_mul_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6a] +v_mul_f16 v5.l, s105, v2.l +// GFX11: v_mul_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x6a] -v_mul_f16 v5, vcc_lo, v2 -// GFX11: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6a] +v_mul_f16 v5.l, vcc_lo, v2.l +// GFX11: v_mul_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x6a] -v_mul_f16 v5, vcc_hi, v2 -// GFX11: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6a] +v_mul_f16 v5.l, vcc_hi, v2.l +// GFX11: v_mul_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x6a] -v_mul_f16 v5, ttmp15, v2 -// GFX11: v_mul_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6a] +v_mul_f16 v5.l, ttmp15, v2.l +// GFX11: v_mul_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x6a] -v_mul_f16 v5, m0, v2 -// GFX11: v_mul_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6a] +v_mul_f16 v5.l, m0, v2.l +// GFX11: v_mul_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x6a] -v_mul_f16 v5, exec_lo, v2 -// GFX11: v_mul_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6a] +v_mul_f16 v5.l, exec_lo, v2.l +// GFX11: v_mul_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x6a] -v_mul_f16 v5, exec_hi, v2 -// GFX11: v_mul_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6a] +v_mul_f16 v5.l, exec_hi, v2.l +// GFX11: v_mul_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x6a] -v_mul_f16 v5, null, v2 -// GFX11: v_mul_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6a] +v_mul_f16 v5.l, null, v2.l +// GFX11: v_mul_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x6a] -v_mul_f16 v5, -1, v2 -// GFX11: v_mul_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6a] +v_mul_f16 v5.l, -1, v2.l +// GFX11: v_mul_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x6a] -v_mul_f16 v5, 0.5, v2 -// GFX11: v_mul_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6a] +v_mul_f16 v5.l, 0.5, v2.l +// GFX11: v_mul_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x6a] -v_mul_f16 v5, src_scc, v2 -// GFX11: v_mul_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6a] +v_mul_f16 v5.l, src_scc, v2.l +// GFX11: v_mul_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x6a] -v_mul_f16 v127, 0xfe0b, v127 -// GFX11: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] +v_mul_f16 v127.l, 0xfe0b, v127.l +// GFX11: v_mul_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] + +v_mul_f16 v5.l, v1.h, v2.l +// GFX11: v_mul_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x6a] + +v_mul_f16 v5.l, v127.h, v2.l +// GFX11: v_mul_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x6a] + +v_mul_f16 v127.l, 0.5, v127.l +// GFX11: v_mul_f16_e32 v127.l, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfe,0x6a] + +v_mul_f16 v5.h, src_scc, v2.h +// GFX11: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b] + +v_mul_f16 v127.h, 0xfe0b, v127.h +// GFX11: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00] v_mul_f32 v5, v1, v2 // GFX11: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s index 00353c4cdcb49..f2d34ab6457af 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s @@ -1227,47 +1227,56 @@ v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl: v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 // GFX11: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30] -v_mul_f16 v5, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] +v_mul_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v1, v2 quad_perm:[0,1,2,3] -// GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] +v_mul_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3] +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] -v_mul_f16 v5, v1, v2 row_mirror -// GFX11: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_mirror +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] -v_mul_f16 v5, v1, v2 row_half_mirror -// GFX11: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_half_mirror +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] -v_mul_f16 v5, v1, v2 row_shl:1 -// GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_shl:1 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] -v_mul_f16 v5, v1, v2 row_shl:15 -// GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_shl:15 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] -v_mul_f16 v5, v1, v2 row_shr:1 -// GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_shr:1 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] -v_mul_f16 v5, v1, v2 row_shr:15 -// GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_shr:15 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] -v_mul_f16 v5, v1, v2 row_ror:1 -// GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_ror:1 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] -v_mul_f16 v5, v1, v2 row_ror:15 -// GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_ror:15 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] -v_mul_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// GFX11: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] -v_mul_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// GFX11: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] +v_mul_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] -v_mul_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// GFX11: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13] +v_mul_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13] -v_mul_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// GFX11: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30] +v_mul_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// GFX11: v_mul_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30] + +v_mul_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x5f,0x01,0x01] + +v_mul_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x6b,0x81,0x60,0x09,0x13] + +v_mul_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: v_mul_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6b,0xff,0x6f,0xf5,0x30] v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0] // GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s index 489e6d8c9d63a..22974f7a4e517 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s @@ -271,14 +271,23 @@ v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 // GFX11: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] -v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] +v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] -v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] +v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] -v_mul_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// GFX11: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] +v_mul_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] + +v_mul_f16 v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x77,0x39,0x05] + +v_mul_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x6b,0x81,0x77,0x39,0x05] + +v_mul_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: v_mul_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x6b,0xff,0x00,0x00,0x00] v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // GFX11: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s index e5504074079e5..6b2e72e4c1146 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s @@ -227,32 +227,59 @@ v_min_f16_e32 v5, v1, v255 v_min_f16_e32 v5, v255, v2 // GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction -v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction -v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction -v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction -v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction -v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction -v_mul_f16_e32 v255, v1, v2 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction -v_mul_f16_e32 v5, v1, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction -v_mul_f16_e32 v5, v255, v2 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction + +v_mul_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction + +v_mul_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction + +v_mul_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction + +v_mul_f16_e32 v255.h, v1.h, v2.h +// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction + +v_mul_f16_e32 v255.l, v1.l, v2.l +// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction + +v_mul_f16_e32 v5.h, v1.h, v255.h +// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction + +v_mul_f16_e32 v5.h, v255.h, v2.h +// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction + +v_mul_f16_e32 v5.l, v1.l, v255.l +// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction + +v_mul_f16_e32 v5.l, v255.l, v2.l +// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction v_sub_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] // GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s index 63394502ec14e..5a87ee451272f 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s @@ -146,32 +146,59 @@ v_min_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] v_min_f16 v5, v255, v2 quad_perm:[3,2,1,0] // GFX11: v_min_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_mul_f16 v255, v1, v2 -// GFX11: v_mul_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] +v_mul_f16 v255.h, v1.h, v2.h +// GFX11: v_mul_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1] ; encoding: [0xff,0x58,0x35,0xd5,0x01,0x05,0x02,0x00] -v_mul_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_mul_f16 v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x58,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_mul_f16 v255.h, v1.h, v2.h quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x58,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v1, v255 -// GFX11: v_mul_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00] +v_mul_f16 v255.l, v1.l, v2.l +// GFX11: v_mul_f16_e64 v255.l, v1.l, v2.l ; encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] -v_mul_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] +v_mul_f16 v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +v_mul_f16 v255.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v255, v2 -// GFX11: v_mul_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x35,0xd5,0xff,0x05,0x02,0x00] +v_mul_f16 v5.h, v1.h, v255.h +// GFX11: v_mul_f16_e64 v5.h, v1.h, v255.h op_sel:[1,1,1] ; encoding: [0x05,0x58,0x35,0xd5,0x01,0xff,0x03,0x00] -v_mul_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] +v_mul_f16 v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.h, v1.h, v255.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] +v_mul_f16 v5.h, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.h, v1.h, v255.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x35,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] + +v_mul_f16 v5.h, v255.h, v2.h +// GFX11: v_mul_f16_e64 v5.h, v255.h, v2.h op_sel:[1,1,1] ; encoding: [0x05,0x58,0x35,0xd5,0xff,0x05,0x02,0x00] + +v_mul_f16 v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.h, v255.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x35,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] + +v_mul_f16 v5.h, v255.h, v2.h quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.h, v255.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x35,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] + +v_mul_f16 v5.l, v1.l, v255.l +// GFX11: v_mul_f16_e64 v5.l, v1.l, v255.l ; encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00] + +v_mul_f16 v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] + +v_mul_f16 v5.l, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] + +v_mul_f16 v5.l, v255.l, v2.l +// GFX11: v_mul_f16_e64 v5.l, v255.l, v2.l ; encoding: [0x05,0x00,0x35,0xd5,0xff,0x05,0x02,0x00] + +v_mul_f16 v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] + +v_mul_f16 v5.l, v255.l, v2.l quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] v_sub_f16 v255.h, v1.h, v2.h // GFX11: v_sub_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1] ; encoding: [0xff,0x58,0x33,0xd5,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s index a63637dc22e3a..529ec730d1278 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s @@ -1112,47 +1112,59 @@ v_mul_dx9_zero_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mas v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 // GFX11: v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x07,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30] -v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_mirror -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_mirror +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_half_mirror -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_half_mirror +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_shl:1 -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shl:1 +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_shl:15 -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shl:15 +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_shr:1 -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shr:1 +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_shr:15 -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shr:15 +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_ror:1 -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_ror:1 +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_ror:15 -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_ror:15 +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] -v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 -// GFX11: v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01] +v_mul_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: v_mul_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01] -v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// GFX11: v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13] +v_mul_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: v_mul_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13] -v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// GFX11: v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30] +v_mul_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: v_mul_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30] + +v_mul_f16_e64_dpp v5.h, v1.h, v2.h row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: v_mul_f16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] + +v_mul_f16_e64_dpp v5.l, |v1.h|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: v_mul_f16_e64_dpp v5.l, |v1.h|, -v2.l op_sel:[1,0,0] mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x09,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01] + +v_mul_f16_e64_dpp v5.l, -v1.l, |v2.h| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: v_mul_f16_e64_dpp v5.l, -v1.l, |v2.h| op_sel:[0,1,0] mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x12,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13] + +v_mul_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: v_mul_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| op_sel:[0,0,1] clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0xc3,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30] v_mul_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] // GFX11: v_mul_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s index 49ee9a7b02bed..e15b2a0c6a444 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s @@ -319,17 +319,29 @@ v_mul_dx9_zero_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 // GFX11: v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x07,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00] -v_mul_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05] +v_mul_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05] -v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// GFX11: v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x35,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05] +v_mul_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: v_mul_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x35,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05] -v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// GFX11: v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x35,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00] +v_mul_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: v_mul_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x35,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00] + +v_mul_f16_e64_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_mul_f16_e64_dpp v5.l, |v1.h|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5.l, |v1.h|, -v2.l op_sel:[1,0,0] mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x09,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05] + +v_mul_f16_e64_dpp v5.l, -v1.l, |v2.h| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: v_mul_f16_e64_dpp v5.l, -v1.l, |v2.h| op_sel:[0,1,0] mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x12,0x35,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05] + +v_mul_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: v_mul_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| op_sel:[0,0,1] clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0xc3,0x35,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00] v_mul_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // GFX11: v_mul_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x08,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s index ee6aa11252609..b50e7ec9f4cf4 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s @@ -1262,50 +1262,59 @@ v_mul_dx9_zero_f32_e64 v5, -src_scc, |vcc_lo| mul:4 v_mul_dx9_zero_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 // GFX11: v_mul_dx9_zero_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x07,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf] -v_mul_f16_e64 v5, v1, v2 -// GFX11: v_mul_f16_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] +v_mul_f16_e64 v5.l, v1.l, v2.l +// GFX11: v_mul_f16_e64 v5.l, v1.l, v2.l ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] -v_mul_f16_e64 v5, v255, v255 -// GFX11: v_mul_f16_e64 v5, v255, v255 ; encoding: [0x05,0x00,0x35,0xd5,0xff,0xff,0x03,0x00] +v_mul_f16_e64 v5.l, v255.l, v255.l +// GFX11: v_mul_f16_e64 v5.l, v255.l, v255.l ; encoding: [0x05,0x00,0x35,0xd5,0xff,0xff,0x03,0x00] -v_mul_f16_e64 v5, s1, s2 -// GFX11: v_mul_f16_e64 v5, s1, s2 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x04,0x00,0x00] +v_mul_f16_e64 v5.l, s1, s2 +// GFX11: v_mul_f16_e64 v5.l, s1, s2 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x04,0x00,0x00] -v_mul_f16_e64 v5, s105, s105 -// GFX11: v_mul_f16_e64 v5, s105, s105 ; encoding: [0x05,0x00,0x35,0xd5,0x69,0xd2,0x00,0x00] +v_mul_f16_e64 v5.l, s105, s105 +// GFX11: v_mul_f16_e64 v5.l, s105, s105 ; encoding: [0x05,0x00,0x35,0xd5,0x69,0xd2,0x00,0x00] -v_mul_f16_e64 v5, vcc_lo, ttmp15 -// GFX11: v_mul_f16_e64 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x35,0xd5,0x6a,0xf6,0x00,0x00] +v_mul_f16_e64 v5.l, vcc_lo, ttmp15 +// GFX11: v_mul_f16_e64 v5.l, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x35,0xd5,0x6a,0xf6,0x00,0x00] -v_mul_f16_e64 v5, vcc_hi, 0xfe0b -// GFX11: v_mul_f16_e64 v5, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x35,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00] +v_mul_f16_e64 v5.l, vcc_hi, 0xfe0b +// GFX11: v_mul_f16_e64 v5.l, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x35,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00] -v_mul_f16_e64 v5, ttmp15, src_scc -// GFX11: v_mul_f16_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x35,0xd5,0x7b,0xfa,0x01,0x00] +v_mul_f16_e64 v5.l, ttmp15, src_scc +// GFX11: v_mul_f16_e64 v5.l, ttmp15, src_scc ; encoding: [0x05,0x00,0x35,0xd5,0x7b,0xfa,0x01,0x00] -v_mul_f16_e64 v5, m0, 0.5 -// GFX11: v_mul_f16_e64 v5, m0, 0.5 ; encoding: [0x05,0x00,0x35,0xd5,0x7d,0xe0,0x01,0x00] +v_mul_f16_e64 v5.l, m0, 0.5 +// GFX11: v_mul_f16_e64 v5.l, m0, 0.5 ; encoding: [0x05,0x00,0x35,0xd5,0x7d,0xe0,0x01,0x00] -v_mul_f16_e64 v5, exec_lo, -1 -// GFX11: v_mul_f16_e64 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x35,0xd5,0x7e,0x82,0x01,0x00] +v_mul_f16_e64 v5.l, exec_lo, -1 +// GFX11: v_mul_f16_e64 v5.l, exec_lo, -1 ; encoding: [0x05,0x00,0x35,0xd5,0x7e,0x82,0x01,0x00] -v_mul_f16_e64 v5, |exec_hi|, null -// GFX11: v_mul_f16_e64 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x35,0xd5,0x7f,0xf8,0x00,0x00] +v_mul_f16_e64 v5.l, |exec_hi|, null +// GFX11: v_mul_f16_e64 v5.l, |exec_hi|, null ; encoding: [0x05,0x01,0x35,0xd5,0x7f,0xf8,0x00,0x00] -v_mul_f16_e64 v5, null, exec_lo -// GFX11: v_mul_f16_e64 v5, null, exec_lo ; encoding: [0x05,0x00,0x35,0xd5,0x7c,0xfc,0x00,0x00] +v_mul_f16_e64 v5.l, null, exec_lo +// GFX11: v_mul_f16_e64 v5.l, null, exec_lo ; encoding: [0x05,0x00,0x35,0xd5,0x7c,0xfc,0x00,0x00] -v_mul_f16_e64 v5, -1, exec_hi -// GFX11: v_mul_f16_e64 v5, -1, exec_hi ; encoding: [0x05,0x00,0x35,0xd5,0xc1,0xfe,0x00,0x00] +v_mul_f16_e64 v5.l, -1, exec_hi +// GFX11: v_mul_f16_e64 v5.l, -1, exec_hi ; encoding: [0x05,0x00,0x35,0xd5,0xc1,0xfe,0x00,0x00] -v_mul_f16_e64 v5, 0.5, -m0 mul:2 -// GFX11: v_mul_f16_e64 v5, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x35,0xd5,0xf0,0xfa,0x00,0x48] +v_mul_f16_e64 v5.l, 0.5, -m0 mul:2 +// GFX11: v_mul_f16_e64 v5.l, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x35,0xd5,0xf0,0xfa,0x00,0x48] -v_mul_f16_e64 v5, -src_scc, |vcc_lo| mul:4 -// GFX11: v_mul_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x35,0xd5,0xfd,0xd4,0x00,0x30] +v_mul_f16_e64 v5.l, -src_scc, |vcc_lo| mul:4 +// GFX11: v_mul_f16_e64 v5.l, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x35,0xd5,0xfd,0xd4,0x00,0x30] -v_mul_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 -// GFX11: v_mul_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00] +v_mul_f16_e64 v255.l, -|0xfe0b|, -|vcc_hi| clamp div:2 +// GFX11: v_mul_f16_e64 v255.l, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00] + +v_mul_f16_e64 v5.l, v1.h, v2.l +// GFX11: v_mul_f16_e64 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x35,0xd5,0x01,0x05,0x02,0x00] + +v_mul_f16_e64 v5.l, v255.l, v255.h +// GFX11: v_mul_f16_e64 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x35,0xd5,0xff,0xff,0x03,0x00] + +v_mul_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| clamp div:2 +// GFX11: v_mul_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,1] clamp div:2 ; encoding: [0xff,0xc3,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00] v_mul_f32_e64 v5, v1, v2 // GFX11: v_mul_f32_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s index 6d07c41de6418..5b91a16e63145 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s @@ -1567,50 +1567,62 @@ v_mul_dx9_zero_f32 v5, src_scc, v2 v_mul_dx9_zero_f32 v255, 0xaf123456, v255 // GFX12: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] -v_mul_f16 v5, v1, v2 -// GFX12: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6a] +v_mul_f16 v5.l, v1.l, v2.l +// GFX12: v_mul_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x6a] -v_mul_f16 v5, v127, v2 -// GFX12: v_mul_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6a] +v_mul_f16 v5.l, v127.l, v2.l +// GFX12: v_mul_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x6a] -v_mul_f16 v5, s1, v2 -// GFX12: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6a] +v_mul_f16 v5.l, s1, v2.l +// GFX12: v_mul_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x6a] -v_mul_f16 v5, s105, v2 -// GFX12: v_mul_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6a] +v_mul_f16 v5.l, s105, v2.l +// GFX12: v_mul_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x6a] -v_mul_f16 v5, vcc_lo, v2 -// GFX12: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6a] +v_mul_f16 v5.l, vcc_lo, v2.l +// GFX12: v_mul_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x6a] -v_mul_f16 v5, vcc_hi, v2 -// GFX12: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6a] +v_mul_f16 v5.l, vcc_hi, v2.l +// GFX12: v_mul_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x6a] -v_mul_f16 v5, ttmp15, v2 -// GFX12: v_mul_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6a] +v_mul_f16 v5.l, ttmp15, v2.l +// GFX12: v_mul_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x6a] -v_mul_f16 v5, m0, v2 -// GFX12: v_mul_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6a] +v_mul_f16 v5.l, m0, v2.l +// GFX12: v_mul_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x6a] -v_mul_f16 v5, exec_lo, v2 -// GFX12: v_mul_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6a] +v_mul_f16 v5.l, exec_lo, v2.l +// GFX12: v_mul_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x6a] -v_mul_f16 v5, exec_hi, v2 -// GFX12: v_mul_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6a] +v_mul_f16 v5.l, exec_hi, v2.l +// GFX12: v_mul_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x6a] -v_mul_f16 v5, null, v2 -// GFX12: v_mul_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6a] +v_mul_f16 v5.l, null, v2.l +// GFX12: v_mul_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x6a] -v_mul_f16 v5, -1, v2 -// GFX12: v_mul_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6a] +v_mul_f16 v5.l, -1, v2.l +// GFX12: v_mul_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x6a] -v_mul_f16 v5, 0.5, v2 -// GFX12: v_mul_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6a] +v_mul_f16 v5.l, 0.5, v2.l +// GFX12: v_mul_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x6a] -v_mul_f16 v5, src_scc, v2 -// GFX12: v_mul_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6a] +v_mul_f16 v5.l, src_scc, v2.l +// GFX12: v_mul_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x6a] -v_mul_f16 v127, 0xfe0b, v127 -// GFX12: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] +v_mul_f16 v127.l, 0xfe0b, v127.l +// GFX12: v_mul_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] + +v_mul_f16 v5.l, v1.h, v2.l +// GFX12: v_mul_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x6a] + +v_mul_f16 v5.l, v127.h, v2.l +// GFX12: v_mul_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x6a] + +v_mul_f16 v5.h, src_scc, v2.h +// GFX12: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b] + +v_mul_f16 v127.h, 0xfe0b, v127.h +// GFX12: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00] v_mul_f32 v5, v1, v2 // GFX12: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s index 2e709832deecc..c7842c2152b93 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s @@ -1122,47 +1122,53 @@ v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl: v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 // GFX12: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30] -v_mul_f16 v5, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] +v_mul_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v1, v2 quad_perm:[0,1,2,3] -// GFX12: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] +v_mul_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3] +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] -v_mul_f16 v5, v1, v2 row_mirror -// GFX12: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_mirror +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] -v_mul_f16 v5, v1, v2 row_half_mirror -// GFX12: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_half_mirror +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] -v_mul_f16 v5, v1, v2 row_shl:1 -// GFX12: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_shl:1 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] -v_mul_f16 v5, v1, v2 row_shl:15 -// GFX12: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_shl:15 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] -v_mul_f16 v5, v1, v2 row_shr:1 -// GFX12: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_shr:1 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] -v_mul_f16 v5, v1, v2 row_shr:15 -// GFX12: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_shr:15 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] -v_mul_f16 v5, v1, v2 row_ror:1 -// GFX12: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_ror:1 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] -v_mul_f16 v5, v1, v2 row_ror:15 -// GFX12: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_ror:15 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] -v_mul_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// GFX12: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] +v_mul_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] -v_mul_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// GFX12: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] +v_mul_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] -v_mul_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// GFX12: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13] +v_mul_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13] -v_mul_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// GFX12: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30] +v_mul_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: v_mul_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30] + +v_mul_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: v_mul_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x6b,0x81,0x60,0x09,0x13] + +v_mul_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: v_mul_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6b,0xff,0x6f,0xf5,0x30] v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0] // GFX12: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s index 2bf74d8d74291..fe1220405f749 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s @@ -253,14 +253,20 @@ v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 // GFX12: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] -v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] +v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] -v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// GFX12: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] +v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] -v_mul_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// GFX12: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] +v_mul_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] + +v_mul_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: v_mul_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x6b,0x81,0x77,0x39,0x05] + +v_mul_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: v_mul_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x6b,0xff,0x00,0x00,0x00] v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // GFX12: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s index 389179b56de31..dd5c96c4a3e4e 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s @@ -217,32 +217,59 @@ v_min_num_f16_e32 v5, v1, v255 v_min_num_f16_e32 v5, v255, v2 // GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction -v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:15: error: invalid operand for instruction -v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:15: error: invalid operand for instruction -v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:15: error: invalid operand for instruction -v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:15: error: invalid operand for instruction -v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction -v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction -v_mul_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:21: error: invalid operand for instruction -v_mul_f16_e32 v5, v1, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:21: error: invalid operand for instruction -v_mul_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction + +v_mul_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction + +v_mul_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:21: error: invalid operand for instruction + +v_mul_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:21: error: invalid operand for instruction + +v_mul_f16_e32 v255.h, v1.h, v2.h +// GFX12: :[[@LINE-1]]:15: error: invalid operand for instruction + +v_mul_f16_e32 v255.l, v1.l, v2.l +// GFX12: :[[@LINE-1]]:15: error: invalid operand for instruction + +v_mul_f16_e32 v5.h, v1.h, v255.h +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction + +v_mul_f16_e32 v5.h, v255.h, v2.h +// GFX12: :[[@LINE-1]]:21: error: invalid operand for instruction + +v_mul_f16_e32 v5.l, v1.l, v255.l +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction + +v_mul_f16_e32 v5.l, v255.l, v2.l +// GFX12: :[[@LINE-1]]:21: error: invalid operand for instruction v_sub_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] // GFX12: :[[@LINE-1]]:15: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s index 3c281c4855985..f5d6b14389a94 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s @@ -136,32 +136,59 @@ v_min_num_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] v_min_num_f16 v5, v255, v2 quad_perm:[3,2,1,0] // GFX12: v_min_num_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_mul_f16 v255, v1, v2 -// GFX12: v_mul_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] +v_mul_f16 v255.h, v1.h, v2.h +// GFX12: v_mul_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1] ; encoding: [0xff,0x58,0x35,0xd5,0x01,0x05,0x02,0x00] -v_mul_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_mul_f16 v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x58,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_mul_f16 v255.h, v1.h, v2.h quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x58,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v1, v255 -// GFX12: v_mul_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00] +v_mul_f16 v255.l, v1.l, v2.l +// GFX12: v_mul_f16_e64 v255.l, v1.l, v2.l ; encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] -v_mul_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] +v_mul_f16 v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +v_mul_f16 v255.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v255, v2 -// GFX12: v_mul_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x35,0xd5,0xff,0x05,0x02,0x00] +v_mul_f16 v5.h, v1.h, v255.h +// GFX12: v_mul_f16_e64 v5.h, v1.h, v255.h op_sel:[1,1,1] ; encoding: [0x05,0x58,0x35,0xd5,0x01,0xff,0x03,0x00] -v_mul_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] +v_mul_f16 v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.h, v1.h, v255.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] +v_mul_f16 v5.h, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.h, v1.h, v255.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x35,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] + +v_mul_f16 v5.h, v255.h, v2.h +// GFX12: v_mul_f16_e64 v5.h, v255.h, v2.h op_sel:[1,1,1] ; encoding: [0x05,0x58,0x35,0xd5,0xff,0x05,0x02,0x00] + +v_mul_f16 v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.h, v255.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x35,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] + +v_mul_f16 v5.h, v255.h, v2.h quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.h, v255.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x35,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] + +v_mul_f16 v5.l, v1.l, v255.l +// GFX12: v_mul_f16_e64 v5.l, v1.l, v255.l ; encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00] + +v_mul_f16 v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] + +v_mul_f16 v5.l, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] + +v_mul_f16 v5.l, v255.l, v2.l +// GFX12: v_mul_f16_e64 v5.l, v255.l, v2.l ; encoding: [0x05,0x00,0x35,0xd5,0xff,0x05,0x02,0x00] + +v_mul_f16 v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] + +v_mul_f16 v5.l, v255.l, v2.l quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] v_sub_f16 v255.h, v1.h, v2.h // GFX12: v_sub_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1] ; encoding: [0xff,0x58,0x33,0xd5,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s index 04caa4a8b5177..f4237ea6e733c 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s @@ -1307,50 +1307,59 @@ v_mul_dx9_zero_f32_e64 v5, -src_scc, |vcc_lo| mul:4 v_mul_dx9_zero_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 // GFX12: v_mul_dx9_zero_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x07,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf] -v_mul_f16_e64 v5, v1, v2 -// GFX12: v_mul_f16_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] +v_mul_f16_e64 v5.l, v1.l, v2.l +// GFX12: v_mul_f16_e64 v5.l, v1.l, v2.l ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] -v_mul_f16_e64 v5, v255, v255 -// GFX12: v_mul_f16_e64 v5, v255, v255 ; encoding: [0x05,0x00,0x35,0xd5,0xff,0xff,0x03,0x00] +v_mul_f16_e64 v5.l, v255.l, v255.l +// GFX12: v_mul_f16_e64 v5.l, v255.l, v255.l ; encoding: [0x05,0x00,0x35,0xd5,0xff,0xff,0x03,0x00] -v_mul_f16_e64 v5, s1, s2 -// GFX12: v_mul_f16_e64 v5, s1, s2 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x04,0x00,0x00] +v_mul_f16_e64 v5.l, s1, s2 +// GFX12: v_mul_f16_e64 v5.l, s1, s2 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x04,0x00,0x00] -v_mul_f16_e64 v5, s105, s105 -// GFX12: v_mul_f16_e64 v5, s105, s105 ; encoding: [0x05,0x00,0x35,0xd5,0x69,0xd2,0x00,0x00] +v_mul_f16_e64 v5.l, s105, s105 +// GFX12: v_mul_f16_e64 v5.l, s105, s105 ; encoding: [0x05,0x00,0x35,0xd5,0x69,0xd2,0x00,0x00] -v_mul_f16_e64 v5, vcc_lo, ttmp15 -// GFX12: v_mul_f16_e64 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x35,0xd5,0x6a,0xf6,0x00,0x00] +v_mul_f16_e64 v5.l, vcc_lo, ttmp15 +// GFX12: v_mul_f16_e64 v5.l, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x35,0xd5,0x6a,0xf6,0x00,0x00] -v_mul_f16_e64 v5, vcc_hi, 0xfe0b -// GFX12: v_mul_f16_e64 v5, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x35,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00] +v_mul_f16_e64 v5.l, vcc_hi, 0xfe0b +// GFX12: v_mul_f16_e64 v5.l, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x35,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00] -v_mul_f16_e64 v5, ttmp15, src_scc -// GFX12: v_mul_f16_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x35,0xd5,0x7b,0xfa,0x01,0x00] +v_mul_f16_e64 v5.l, ttmp15, src_scc +// GFX12: v_mul_f16_e64 v5.l, ttmp15, src_scc ; encoding: [0x05,0x00,0x35,0xd5,0x7b,0xfa,0x01,0x00] -v_mul_f16_e64 v5, m0, 0.5 -// GFX12: v_mul_f16_e64 v5, m0, 0.5 ; encoding: [0x05,0x00,0x35,0xd5,0x7d,0xe0,0x01,0x00] +v_mul_f16_e64 v5.l, m0, 0.5 +// GFX12: v_mul_f16_e64 v5.l, m0, 0.5 ; encoding: [0x05,0x00,0x35,0xd5,0x7d,0xe0,0x01,0x00] -v_mul_f16_e64 v5, exec_lo, -1 -// GFX12: v_mul_f16_e64 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x35,0xd5,0x7e,0x82,0x01,0x00] +v_mul_f16_e64 v5.l, exec_lo, -1 +// GFX12: v_mul_f16_e64 v5.l, exec_lo, -1 ; encoding: [0x05,0x00,0x35,0xd5,0x7e,0x82,0x01,0x00] -v_mul_f16_e64 v5, |exec_hi|, null -// GFX12: v_mul_f16_e64 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x35,0xd5,0x7f,0xf8,0x00,0x00] +v_mul_f16_e64 v5.l, |exec_hi|, null +// GFX12: v_mul_f16_e64 v5.l, |exec_hi|, null ; encoding: [0x05,0x01,0x35,0xd5,0x7f,0xf8,0x00,0x00] -v_mul_f16_e64 v5, null, exec_lo -// GFX12: v_mul_f16_e64 v5, null, exec_lo ; encoding: [0x05,0x00,0x35,0xd5,0x7c,0xfc,0x00,0x00] +v_mul_f16_e64 v5.l, null, exec_lo +// GFX12: v_mul_f16_e64 v5.l, null, exec_lo ; encoding: [0x05,0x00,0x35,0xd5,0x7c,0xfc,0x00,0x00] -v_mul_f16_e64 v5, -1, exec_hi -// GFX12: v_mul_f16_e64 v5, -1, exec_hi ; encoding: [0x05,0x00,0x35,0xd5,0xc1,0xfe,0x00,0x00] +v_mul_f16_e64 v5.l, -1, exec_hi +// GFX12: v_mul_f16_e64 v5.l, -1, exec_hi ; encoding: [0x05,0x00,0x35,0xd5,0xc1,0xfe,0x00,0x00] -v_mul_f16_e64 v5, 0.5, -m0 mul:2 -// GFX12: v_mul_f16_e64 v5, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x35,0xd5,0xf0,0xfa,0x00,0x48] +v_mul_f16_e64 v5.l, 0.5, -m0 mul:2 +// GFX12: v_mul_f16_e64 v5.l, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x35,0xd5,0xf0,0xfa,0x00,0x48] -v_mul_f16_e64 v5, -src_scc, |vcc_lo| mul:4 -// GFX12: v_mul_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x35,0xd5,0xfd,0xd4,0x00,0x30] +v_mul_f16_e64 v5.l, -src_scc, |vcc_lo| mul:4 +// GFX12: v_mul_f16_e64 v5.l, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x35,0xd5,0xfd,0xd4,0x00,0x30] -v_mul_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 -// GFX12: v_mul_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00] +v_mul_f16_e64 v255.l, -|0xfe0b|, -|vcc_hi| clamp div:2 +// GFX12: v_mul_f16_e64 v255.l, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00] + +v_mul_f16_e64 v5.l, v1.h, v2.l +// GFX12: v_mul_f16_e64 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x35,0xd5,0x01,0x05,0x02,0x00] + +v_mul_f16_e64 v5.l, v255.l, v255.h +// GFX12: v_mul_f16_e64 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x35,0xd5,0xff,0xff,0x03,0x00] + +v_mul_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| clamp div:2 +// GFX12: v_mul_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,1] clamp div:2 ; encoding: [0xff,0xc3,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00] v_mul_f32_e64 v5, v1, v2 // GFX12: v_mul_f32_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s index 7991b87583aac..1a5ba1c2c73d3 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s @@ -1142,53 +1142,65 @@ v_mul_dx9_zero_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mas v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 // GFX12: v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x07,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30] -v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_mirror -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_mirror +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_half_mirror -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_half_mirror +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_shl:1 -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shl:1 +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_shl:15 -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shl:15 +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, s2 row_shl:15 -// GFX12: v_mul_f16_e64_dpp v5, v1, s2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x00,0x00,0x01,0x0f,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, s2 row_shl:15 +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, s2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x00,0x00,0x01,0x0f,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, 2.0 row_shl:15 -// GFX12: v_mul_f16_e64_dpp v5, v1, 2.0 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0xe8,0x01,0x00,0x01,0x0f,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, 2.0 row_shl:15 +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, 2.0 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0xe8,0x01,0x00,0x01,0x0f,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_shr:1 -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shr:1 +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_shr:15 -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shr:15 +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_ror:1 -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_ror:1 +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_ror:15 -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_ror:15 +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] -v_mul_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] -v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 -// GFX12: v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01] +v_mul_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: v_mul_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01] -v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// GFX12: v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13] +v_mul_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: v_mul_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13] -v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// GFX12: v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30] +v_mul_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: v_mul_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30] + +v_mul_f16_e64_dpp v5.h, v1.h, v2.h row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: v_mul_f16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] + +v_mul_f16_e64_dpp v5.l, |v1.h|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: v_mul_f16_e64_dpp v5.l, |v1.h|, -v2.l op_sel:[1,0,0] mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x09,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01] + +v_mul_f16_e64_dpp v5.l, -v1.l, |v2.h| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: v_mul_f16_e64_dpp v5.l, -v1.l, |v2.h| op_sel:[0,1,0] mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x12,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13] + +v_mul_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: v_mul_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| op_sel:[0,0,1] clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0xc3,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30] v_mul_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] // GFX12: v_mul_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s index 05d3ee1fa853a..95d92b8a6089f 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s @@ -440,23 +440,35 @@ v_mul_dx9_zero_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 // GFX12: v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x07,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00] -v_mul_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_mul_f16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_mul_f16_e64_dpp v5, v1, s2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, v1, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] +v_mul_f16_e64_dpp v5.l, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] -v_mul_f16_e64_dpp v5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +v_mul_f16_e64_dpp v5.l, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] -v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05] +v_mul_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05] -v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// GFX12: v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x35,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05] +v_mul_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: v_mul_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x35,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05] -v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// GFX12: v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x35,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00] +v_mul_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: v_mul_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x35,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00] + +v_mul_f16_e64_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_mul_f16_e64_dpp v5.l, |v1.h|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5.l, |v1.h|, -v2.l op_sel:[1,0,0] mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x09,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05] + +v_mul_f16_e64_dpp v5.l, -v1.l, |v2.h| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: v_mul_f16_e64_dpp v5.l, -v1.l, |v2.h| op_sel:[0,1,0] mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x12,0x35,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05] + +v_mul_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: v_mul_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| op_sel:[0,0,1] clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0xc3,0x35,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00] v_mul_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // GFX12: v_mul_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x08,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]