From 6b852f9d05a1997167ed3b337559b3d43479b147 Mon Sep 17 00:00:00 2001
From: jofrn <jofernau@amd.com>
Date: Tue, 10 Dec 2024 11:53:21 -0800
Subject: [PATCH 01/12] [LiveVariables] Mark use as implicit-def if def is a
 subregister

LiveVariables will mark instructions with their implicit subregister
uses. However, it will miss marking the subregister as an implicit-def
if its own definition is a subregister of it, i.e.
`$r3 = OP val, implicit-def $r0_r1_r2_r3, ..., implicit $r2_r3`,
which defines $sr3 on the same line it is used.

This change ensures such uses are marked as implicit-def, i.e.
`$r3 = OP val, implicit-def $r0_r1_r2_r3, ..., implicit-def $r2_r3`.
---
 llvm/lib/CodeGen/LiveVariables.cpp            | 17 +++++--
 .../CodeGen/AMDGPU/implicitdef-subreg.mir     | 46 +++++++++++++++++++
 2 files changed, 60 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir

diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index f17d60dc22dda..ec6c360561bd9 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -277,11 +277,22 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
           continue;
         if (PartDefRegs.count(SubReg))
           continue;
+
+        // Check if SubReg is defined at LastPartialDef.
+        bool IsDefinedHere = false;
+        for (int I = 0; I < LastPartialDef->getNumOperands(); ++I) {
+          const auto MO = LastPartialDef->getOperand(I);
+          if (!MO.isReg() || !MO.isDef())
+            continue;
+          if (TRI->isSubRegister(SubReg, MO.getReg())) {
+            IsDefinedHere = true;
+            break;
+          }
+        }
         // This part of Reg was defined before the last partial def. It's killed
         // here.
-        LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
-                                                             false/*IsDef*/,
-                                                             true/*IsImp*/));
+        LastPartialDef->addOperand(
+            MachineOperand::CreateReg(SubReg, IsDefinedHere, true /*IsImp*/));
         PhysRegDef[SubReg] = LastPartialDef;
         for (MCPhysReg SS : TRI->subregs(SubReg))
           Processed.insert(SS);
diff --git a/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir b/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
new file mode 100644
index 0000000000000..4f5bc49dabfda
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn --run-pass=livevars -o - %s | FileCheck %s
+---
+name:            sgpr_copy
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: sgpr_copy
+    ; CHECK: %sval:sreg_32 = S_MOV_B32 0
+    ; CHECK-NEXT: $sgpr0 = COPY %sval
+    ; CHECK-NEXT: $sgpr1 = COPY %sval
+    ; CHECK-NEXT: $sgpr2 = COPY %sval
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
+    ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+
+    %sval:sreg_32 = S_MOV_B32 0
+
+    $sgpr0 = COPY %sval
+    $sgpr1 = COPY %sval
+    $sgpr2 = COPY %sval
+    $sgpr3 = COPY %sval
+    $sgpr30_sgpr31 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+
+...
+---
+name:            vgpr_copy
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: vgpr_copy
+    ; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK-NEXT: $vgpr0 = COPY %vval
+    ; CHECK-NEXT: $vgpr1 = COPY %vval
+    ; CHECK-NEXT: $vgpr2 = COPY %vval
+    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr0_vgpr1, implicit $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
+
+    %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+
+    $vgpr0 = COPY %vval
+    $vgpr1 = COPY %vval
+    $vgpr2 = COPY %vval
+    $vgpr3 = COPY %vval
+    %0:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+
+...

From 0208eb91b91c5b211d661853cd3a12b6b88e0701 Mon Sep 17 00:00:00 2001
From: jofrn <jofernau@amd.com>
Date: Wed, 11 Dec 2024 01:24:12 -0800
Subject: [PATCH 02/12] Rewrite loop to be modifiesRegister

This also causes superregisters to be marked as implicit-def.
---
 llvm/lib/CodeGen/LiveVariables.cpp              | 11 +----------
 llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir  |  2 +-
 llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir |  8 ++++----
 3 files changed, 6 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index ec6c360561bd9..39d2658030898 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -279,16 +279,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
           continue;
 
         // Check if SubReg is defined at LastPartialDef.
-        bool IsDefinedHere = false;
-        for (int I = 0; I < LastPartialDef->getNumOperands(); ++I) {
-          const auto MO = LastPartialDef->getOperand(I);
-          if (!MO.isReg() || !MO.isDef())
-            continue;
-          if (TRI->isSubRegister(SubReg, MO.getReg())) {
-            IsDefinedHere = true;
-            break;
-          }
-        }
+        bool IsDefinedHere = LastPartialDef->modifiesRegister(SubReg, TRI);
         // This part of Reg was defined before the last partial def. It's killed
         // here.
         LastPartialDef->addOperand(
diff --git a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
index a10d7588cb442..c2fba541bdd1e 100644
--- a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
+++ b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
@@ -756,7 +756,7 @@ body:             |
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1, implicit $w1_hi :: (load (s32))
-    ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2, implicit $w2_hi :: (load (s32))
+    ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2, implicit-def $w2_hi :: (load (s32))
     ; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
     ; CHECK-NEXT: RET undef $lr
     early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
diff --git a/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir b/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
index 4f5bc49dabfda..dd6352586f2e5 100644
--- a/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
@@ -5,14 +5,14 @@ name:            sgpr_copy
 tracksRegLiveness: true
 body:             |
   bb.0:
+
     ; CHECK-LABEL: name: sgpr_copy
     ; CHECK: %sval:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: $sgpr0 = COPY %sval
     ; CHECK-NEXT: $sgpr1 = COPY %sval
     ; CHECK-NEXT: $sgpr2 = COPY %sval
-    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr1, implicit-def $sgpr2, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
     ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
-
     %sval:sreg_32 = S_MOV_B32 0
 
     $sgpr0 = COPY %sval
@@ -27,14 +27,14 @@ name:            vgpr_copy
 tracksRegLiveness: true
 body:             |
   bb.0:
+
     ; CHECK-LABEL: name: vgpr_copy
     ; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     ; CHECK-NEXT: $vgpr0 = COPY %vval
     ; CHECK-NEXT: $vgpr1 = COPY %vval
     ; CHECK-NEXT: $vgpr2 = COPY %vval
-    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr0_vgpr1, implicit $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr0_vgpr1, implicit-def $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
-
     %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
     $vgpr0 = COPY %vval

From e0cd95a70d8d348e2364fee4479f953dcb21f775 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau@amd.com>
Date: Wed, 11 Dec 2024 02:52:19 -0800
Subject: [PATCH 03/12] Add ll test

---
 .../test/CodeGen/AMDGPU/fncall-implicitdef.ll | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll

diff --git a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
new file mode 100644
index 0000000000000..9c053219c0b31
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O1 %s -o - | FileCheck %s
+
+define amdgpu_ps <4 x float> @caller(ptr %1) {
+; CHECK-LABEL: caller:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    flat_load_dword v1, v[0:1]
+; CHECK-NEXT:    s_getpc_b64 s[0:1]
+; CHECK-NEXT:    s_add_u32 s0, s0, fn@gotpcrel32@lo+4
+; CHECK-NEXT:    s_addc_u32 s1, s1, fn@gotpcrel32@hi+12
+; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
+; CHECK-NEXT:    s_mov_b32 s0, 0
+; CHECK-NEXT:    s_mov_b32 s1, 0
+; CHECK-NEXT:    s_mov_b32 s2, 0
+; CHECK-NEXT:    s_mov_b64 s[8:9], 36
+; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    s_mov_b32 s3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    s_mov_b32 s32, 0
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_swappc_b64 s[30:31], s[4:5]
+; CHECK-NEXT:    ; return to shader part epilog
+  %L = load i32, ptr %1, align 4
+  %R = call <4 x float> @fn(<4 x i32> zeroinitializer, i32 0, i32 %L, i32 0)
+  ret <4 x float> %R
+}
+
+declare <4 x float> @fn(<4 x i32> inreg, i32, i32, i32)

From 1fa40b79512173fcff5d27a075e2c75dd045d064 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau@amd.com>
Date: Thu, 12 Dec 2024 07:52:53 -0800
Subject: [PATCH 04/12] Rename test, use named value & declare hidden

---
 llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll     | 14 ++++++--------
 ...icitdef-subreg.mir => livevars-implicitdef.mir} |  0
 2 files changed, 6 insertions(+), 8 deletions(-)
 rename llvm/test/CodeGen/AMDGPU/{implicitdef-subreg.mir => livevars-implicitdef.mir} (100%)

diff --git a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
index 9c053219c0b31..551ae4dd3faae 100644
--- a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
+++ b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
@@ -1,14 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O1 %s -o - | FileCheck %s
 
-define amdgpu_ps <4 x float> @caller(ptr %1) {
+define amdgpu_ps <4 x float> @caller(ptr %ptr) {
 ; CHECK-LABEL: caller:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    flat_load_dword v1, v[0:1]
-; CHECK-NEXT:    s_getpc_b64 s[0:1]
-; CHECK-NEXT:    s_add_u32 s0, s0, fn@gotpcrel32@lo+4
-; CHECK-NEXT:    s_addc_u32 s1, s1, fn@gotpcrel32@hi+12
-; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
 ; CHECK-NEXT:    s_mov_b32 s0, 0
 ; CHECK-NEXT:    s_mov_b32 s1, 0
 ; CHECK-NEXT:    s_mov_b32 s2, 0
@@ -17,12 +13,14 @@ define amdgpu_ps <4 x float> @caller(ptr %1) {
 ; CHECK-NEXT:    s_mov_b32 s3, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    s_mov_b32 s32, 0
-; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_getpc_b64 s[4:5]
+; CHECK-NEXT:    s_add_u32 s4, s4, fn@rel32@lo+4
+; CHECK-NEXT:    s_addc_u32 s5, s5, fn@rel32@hi+12
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; CHECK-NEXT:    ; return to shader part epilog
-  %L = load i32, ptr %1, align 4
+  %L = load i32, ptr %ptr, align 4
   %R = call <4 x float> @fn(<4 x i32> zeroinitializer, i32 0, i32 %L, i32 0)
   ret <4 x float> %R
 }
 
-declare <4 x float> @fn(<4 x i32> inreg, i32, i32, i32)
+declare hidden <4 x float> @fn(<4 x i32> inreg, i32, i32, i32)
diff --git a/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
similarity index 100%
rename from llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
rename to llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir

From ebc5d0c137ebd3f9b0ffc331bf4653c5994aadad Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau@amd.com>
Date: Wed, 18 Dec 2024 01:47:18 -0800
Subject: [PATCH 05/12] Delete PartDefRegs part of HandlePhysRegUse

---
 llvm/include/llvm/CodeGen/LiveVariables.h     |  6 ++--
 llvm/lib/CodeGen/LiveVariables.cpp            | 36 ++-----------------
 .../test/CodeGen/AArch64/ldrpre-ldr-merge.mir |  2 +-
 .../CodeGen/AMDGPU/livevars-implicitdef.mir   |  4 +--
 4 files changed, 7 insertions(+), 41 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/LiveVariables.h b/llvm/include/llvm/CodeGen/LiveVariables.h
index 89d1b5edf3fa6..6f7be0c30b8a6 100644
--- a/llvm/include/llvm/CodeGen/LiveVariables.h
+++ b/llvm/include/llvm/CodeGen/LiveVariables.h
@@ -164,10 +164,8 @@ class LiveVariables {
   MachineInstr *FindLastRefOrPartRef(Register Reg);
 
   /// FindLastPartialDef - Return the last partial def of the specified
-  /// register. Also returns the sub-registers that're defined by the
-  /// instruction.
-  MachineInstr *FindLastPartialDef(Register Reg,
-                                   SmallSet<unsigned, 4> &PartDefRegs);
+  /// register.
+  MachineInstr *FindLastPartialDef(Register Reg);
 
   /// analyzePHINodes - Gather information about the PHI nodes in here. In
   /// particular, we want to map the variable information of a virtual
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 39d2658030898..cfe3038f7fb2a 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -216,9 +216,7 @@ void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
 /// FindLastPartialDef - Return the last partial def of the specified register.
 /// Also returns the sub-registers that're defined by the instruction.
 MachineInstr *
-LiveVariables::FindLastPartialDef(Register Reg,
-                                  SmallSet<unsigned, 4> &PartDefRegs) {
-  unsigned LastDefReg = 0;
+LiveVariables::FindLastPartialDef(Register Reg) {
   unsigned LastDefDist = 0;
   MachineInstr *LastDef = nullptr;
   for (MCPhysReg SubReg : TRI->subregs(Reg)) {
@@ -227,7 +225,6 @@ LiveVariables::FindLastPartialDef(Register Reg,
       continue;
     unsigned Dist = DistanceMap[Def];
     if (Dist > LastDefDist) {
-      LastDefReg  = SubReg;
       LastDef     = Def;
       LastDefDist = Dist;
     }
@@ -236,16 +233,6 @@ LiveVariables::FindLastPartialDef(Register Reg,
   if (!LastDef)
     return nullptr;
 
-  PartDefRegs.insert(LastDefReg);
-  for (MachineOperand &MO : LastDef->all_defs()) {
-    if (MO.getReg() == 0)
-      continue;
-    Register DefReg = MO.getReg();
-    if (TRI->isSubRegister(Reg, DefReg)) {
-      for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg))
-        PartDefRegs.insert(SubReg);
-    }
-  }
   return LastDef;
 }
 
@@ -264,30 +251,11 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
     // ...
     //    = EAX
     // All of the sub-registers must have been defined before the use of Reg!
-    SmallSet<unsigned, 4> PartDefRegs;
-    MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
+    MachineInstr *LastPartialDef = FindLastPartialDef(Reg);
     // If LastPartialDef is NULL, it must be using a livein register.
     if (LastPartialDef) {
       LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
                                                            true/*IsImp*/));
-      PhysRegDef[Reg] = LastPartialDef;
-      SmallSet<unsigned, 8> Processed;
-      for (MCPhysReg SubReg : TRI->subregs(Reg)) {
-        if (Processed.count(SubReg))
-          continue;
-        if (PartDefRegs.count(SubReg))
-          continue;
-
-        // Check if SubReg is defined at LastPartialDef.
-        bool IsDefinedHere = LastPartialDef->modifiesRegister(SubReg, TRI);
-        // This part of Reg was defined before the last partial def. It's killed
-        // here.
-        LastPartialDef->addOperand(
-            MachineOperand::CreateReg(SubReg, IsDefinedHere, true /*IsImp*/));
-        PhysRegDef[SubReg] = LastPartialDef;
-        for (MCPhysReg SS : TRI->subregs(SubReg))
-          Processed.insert(SS);
-      }
     }
   } else if (LastDef && !PhysRegUse[Reg] &&
              !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
diff --git a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
index c2fba541bdd1e..8a5e0f6aa843a 100644
--- a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
+++ b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
@@ -756,7 +756,7 @@ body:             |
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1, implicit $w1_hi :: (load (s32))
-    ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2, implicit-def $w2_hi :: (load (s32))
+    ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2 :: (load (s32))
     ; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
     ; CHECK-NEXT: RET undef $lr
     early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
diff --git a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
index dd6352586f2e5..8177568d0a4ed 100644
--- a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
+++ b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
@@ -11,7 +11,7 @@ body:             |
     ; CHECK-NEXT: $sgpr0 = COPY %sval
     ; CHECK-NEXT: $sgpr1 = COPY %sval
     ; CHECK-NEXT: $sgpr2 = COPY %sval
-    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr1, implicit-def $sgpr2, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
     ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
     %sval:sreg_32 = S_MOV_B32 0
 
@@ -33,7 +33,7 @@ body:             |
     ; CHECK-NEXT: $vgpr0 = COPY %vval
     ; CHECK-NEXT: $vgpr1 = COPY %vval
     ; CHECK-NEXT: $vgpr2 = COPY %vval
-    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr0_vgpr1, implicit-def $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
     %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 

From 7b3266ed20e0665eb634f662a5b17b03654c031e Mon Sep 17 00:00:00 2001
From: Joey F <jofernau@amd.com>
Date: Sat, 10 May 2025 14:24:31 -0400
Subject: [PATCH 06/12] clang-format

---
 llvm/lib/CodeGen/LiveVariables.cpp | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 0fe610d09a935..eb5651ca7fc63 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -215,8 +215,7 @@ void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
 
 /// FindLastPartialDef - Return the last partial def of the specified register.
 /// Also returns the sub-registers that're defined by the instruction.
-MachineInstr *
-LiveVariables::FindLastPartialDef(Register Reg) {
+MachineInstr *LiveVariables::FindLastPartialDef(Register Reg) {
   unsigned LastDefDist = 0;
   MachineInstr *LastDef = nullptr;
   for (MCPhysReg SubReg : TRI->subregs(Reg)) {
@@ -254,8 +253,8 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
     MachineInstr *LastPartialDef = FindLastPartialDef(Reg);
     // If LastPartialDef is NULL, it must be using a livein register.
     if (LastPartialDef) {
-      LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
-                                                           true/*IsImp*/));
+      LastPartialDef->addOperand(
+          MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
     }
   } else if (LastDef && !PhysRegUse[Reg.id()] &&
              !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))

From a9d1662dc9ef6865097c403cad9334b83d7476a0 Mon Sep 17 00:00:00 2001
From: Joey F <jofernau@amd.com>
Date: Sat, 10 May 2025 19:45:03 -0400
Subject: [PATCH 07/12] Add tests and comments

---
 .../CodeGen/AMDGPU/livevars-implicitdef.mir   | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
index 8177568d0a4ed..f25a64d41e072 100644
--- a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
+++ b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
@@ -1,6 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple=amdgcn --run-pass=livevars -o - %s | FileCheck %s
 ---
+# Check that super register is implicitly defined for an sgpr copy.
 name:            sgpr_copy
 tracksRegLiveness: true
 body:             |
@@ -23,6 +24,7 @@ body:             |
 
 ...
 ---
+# Check that super register is implicitly defined for a vgpr vector copy.
 name:            vgpr_copy
 tracksRegLiveness: true
 body:             |
@@ -44,3 +46,45 @@ body:             |
     %0:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
 
 ...
+---
+# Check that super register is implicitly defined when there is a hole.
+name:            sgpr_copy_hole
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: sgpr_copy_hole
+    ; CHECK: %sval:sreg_32 = S_MOV_B32 0
+    ; CHECK-NEXT: $sgpr0 = COPY %sval
+    ; CHECK-NEXT: $sgpr2 = COPY %sval
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+    %sval:sreg_32 = S_MOV_B32 0
+
+    $sgpr0 = COPY %sval
+    $sgpr2 = COPY %sval
+    $sgpr3 = COPY %sval
+    $sgpr30_sgpr31 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+
+...
+---
+# Check that super register is imp-def when a pair interrupts the sequence.
+name:            vgpr_copy_pair
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: vgpr_copy_pair
+    ; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK-NEXT: $vgpr0 = COPY %vval
+    ; CHECK-NEXT: $vgpr1 = COPY %vval
+    ; CHECK-NEXT: $vgpr2 = COPY %vval, implicit-def $vgpr1_vgpr2
+    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1_vgpr2
+    ; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
+    %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+
+    $vgpr0 = COPY %vval
+    $vgpr1 = COPY %vval
+    $vgpr2 = COPY %vval
+    $vgpr3 = COPY %vval
+    %0:vgpr_32 = COPY $vgpr1_vgpr2
+    %1:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3

From 0ecabb7a125fa98acce79967384c610101eea468 Mon Sep 17 00:00:00 2001
From: Joey F <jofernau@amd.com>
Date: Sat, 10 May 2025 20:27:35 -0400
Subject: [PATCH 08/12] Update test after rebase

---
 llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
index 551ae4dd3faae..28fbef9023774 100644
--- a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
+++ b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
@@ -8,14 +8,14 @@ define amdgpu_ps <4 x float> @caller(ptr %ptr) {
 ; CHECK-NEXT:    s_mov_b32 s0, 0
 ; CHECK-NEXT:    s_mov_b32 s1, 0
 ; CHECK-NEXT:    s_mov_b32 s2, 0
+; CHECK-NEXT:    s_getpc_b64 s[4:5]
+; CHECK-NEXT:    s_add_u32 s4, s4, fn@rel32@lo+4
+; CHECK-NEXT:    s_addc_u32 s5, s5, fn@rel32@hi+12
 ; CHECK-NEXT:    s_mov_b64 s[8:9], 36
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; CHECK-NEXT:    s_mov_b32 s3, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    s_mov_b32 s32, 0
-; CHECK-NEXT:    s_getpc_b64 s[4:5]
-; CHECK-NEXT:    s_add_u32 s4, s4, fn@rel32@lo+4
-; CHECK-NEXT:    s_addc_u32 s5, s5, fn@rel32@hi+12
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; CHECK-NEXT:    ; return to shader part epilog
   %L = load i32, ptr %ptr, align 4

From 6669df1058464a5b3cd1f9432828e7c893de6669 Mon Sep 17 00:00:00 2001
From: Joey F <jofernau@amd.com>
Date: Tue, 27 May 2025 11:28:48 -0400
Subject: [PATCH 09/12] Respond to comments

---
 llvm/lib/CodeGen/LiveVariables.cpp            | 11 ++++----
 .../test/CodeGen/AMDGPU/fncall-implicitdef.ll | 11 ++++----
 .../CodeGen/AMDGPU/livevars-implicitdef.mir   | 27 ++++++++++---------
 3 files changed, 24 insertions(+), 25 deletions(-)

diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index eb5651ca7fc63..4f0567cefbf3d 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -214,7 +214,6 @@ void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
 }
 
 /// FindLastPartialDef - Return the last partial def of the specified register.
-/// Also returns the sub-registers that're defined by the instruction.
 MachineInstr *LiveVariables::FindLastPartialDef(Register Reg) {
   unsigned LastDefDist = 0;
   MachineInstr *LastDef = nullptr;
@@ -250,12 +249,12 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
     // ...
     //    = EAX
     // All of the sub-registers must have been defined before the use of Reg!
-    MachineInstr *LastPartialDef = FindLastPartialDef(Reg);
+    // MachineInstr *LastPartialDef = FindLastPartialDef(Reg);
     // If LastPartialDef is NULL, it must be using a livein register.
-    if (LastPartialDef) {
-      LastPartialDef->addOperand(
-          MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
-    }
+    // if (LastPartialDef) {
+    //   LastPartialDef->addOperand(
+    //     MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
+    // }
   } else if (LastDef && !PhysRegUse[Reg.id()] &&
              !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
     // Last def defines the super register, add an implicit def of reg.
diff --git a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
index 28fbef9023774..87d05e3e2b4b9 100644
--- a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
+++ b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
@@ -1,19 +1,18 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O1 %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -O1 %s -o - | FileCheck %s
 
 define amdgpu_ps <4 x float> @caller(ptr %ptr) {
 ; CHECK-LABEL: caller:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    flat_load_dword v1, v[0:1]
+; CHECK-NEXT:    s_mov_b32 s5, fn@abs32@hi
+; CHECK-NEXT:    s_mov_b32 s4, fn@abs32@lo
+; CHECK-NEXT:    s_mov_b64 s[8:9], 0
 ; CHECK-NEXT:    s_mov_b32 s0, 0
 ; CHECK-NEXT:    s_mov_b32 s1, 0
 ; CHECK-NEXT:    s_mov_b32 s2, 0
-; CHECK-NEXT:    s_getpc_b64 s[4:5]
-; CHECK-NEXT:    s_add_u32 s4, s4, fn@rel32@lo+4
-; CHECK-NEXT:    s_addc_u32 s5, s5, fn@rel32@hi+12
-; CHECK-NEXT:    s_mov_b64 s[8:9], 36
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; CHECK-NEXT:    s_mov_b32 s3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    s_mov_b32 s32, 0
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
index f25a64d41e072..18aeb2527b1a3 100644
--- a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
+++ b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple=amdgcn --run-pass=livevars -o - %s | FileCheck %s
 ---
-# Check that super register is implicitly defined for an sgpr copy.
+# Check that super register is defined for an sgpr copy.
 name:            sgpr_copy
 tracksRegLiveness: true
 body:             |
@@ -12,19 +12,19 @@ body:             |
     ; CHECK-NEXT: $sgpr0 = COPY %sval
     ; CHECK-NEXT: $sgpr1 = COPY %sval
     ; CHECK-NEXT: $sgpr2 = COPY %sval
-    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
-    ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval
+    ; CHECK-NEXT: SI_RETURN implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
     %sval:sreg_32 = S_MOV_B32 0
 
     $sgpr0 = COPY %sval
     $sgpr1 = COPY %sval
     $sgpr2 = COPY %sval
     $sgpr3 = COPY %sval
-    $sgpr30_sgpr31 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    SI_RETURN implicit $sgpr0_sgpr1_sgpr2_sgpr3
 
 ...
 ---
-# Check that super register is implicitly defined for a vgpr vector copy.
+# Check that super register is defined for a vgpr vector copy.
 name:            vgpr_copy
 tracksRegLiveness: true
 body:             |
@@ -35,7 +35,7 @@ body:             |
     ; CHECK-NEXT: $vgpr0 = COPY %vval
     ; CHECK-NEXT: $vgpr1 = COPY %vval
     ; CHECK-NEXT: $vgpr2 = COPY %vval
-    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: $vgpr3 = COPY killed %vval
     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
     %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
@@ -47,7 +47,7 @@ body:             |
 
 ...
 ---
-# Check that super register is implicitly defined when there is a hole.
+# Check that super register is defined when there is a hole.
 name:            sgpr_copy_hole
 tracksRegLiveness: true
 body:             |
@@ -56,18 +56,18 @@ body:             |
     ; CHECK: %sval:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: $sgpr0 = COPY %sval
     ; CHECK-NEXT: $sgpr2 = COPY %sval
-    ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
-    ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: $sgpr3 = COPY killed %sval
+    ; CHECK-NEXT: SI_RETURN implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
     %sval:sreg_32 = S_MOV_B32 0
 
     $sgpr0 = COPY %sval
     $sgpr2 = COPY %sval
     $sgpr3 = COPY %sval
-    $sgpr30_sgpr31 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    SI_RETURN implicit $sgpr0_sgpr1_sgpr2_sgpr3
 
 ...
 ---
-# Check that super register is imp-def when a pair interrupts the sequence.
+# Check that super register is defined when a pair interrupts the sequence.
 name:            vgpr_copy_pair
 tracksRegLiveness: true
 body:             |
@@ -76,8 +76,8 @@ body:             |
     ; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     ; CHECK-NEXT: $vgpr0 = COPY %vval
     ; CHECK-NEXT: $vgpr1 = COPY %vval
-    ; CHECK-NEXT: $vgpr2 = COPY %vval, implicit-def $vgpr1_vgpr2
-    ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: $vgpr2 = COPY %vval
+    ; CHECK-NEXT: $vgpr3 = COPY killed %vval
     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1_vgpr2
     ; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
     %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
@@ -88,3 +88,4 @@ body:             |
     $vgpr3 = COPY %vval
     %0:vgpr_32 = COPY $vgpr1_vgpr2
     %1:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+...

From 5672eaed61272c4266bea6940fbc0dc941883ccc Mon Sep 17 00:00:00 2001
From: Joey F <jofernau@amd.com>
Date: Fri, 30 May 2025 15:32:56 -0400
Subject: [PATCH 10/12] Added FindLastPartialDef back

---
 llvm/lib/CodeGen/LiveVariables.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 4f0567cefbf3d..052400e99b4aa 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -249,12 +249,12 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
     // ...
     //    = EAX
     // All of the sub-registers must have been defined before the use of Reg!
-    // MachineInstr *LastPartialDef = FindLastPartialDef(Reg);
+    MachineInstr *LastPartialDef = FindLastPartialDef(Reg);
     // If LastPartialDef is NULL, it must be using a livein register.
-    // if (LastPartialDef) {
-    //   LastPartialDef->addOperand(
-    //     MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
-    // }
+    if (LastPartialDef) {
+      LastPartialDef->addOperand(
+        MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
+    }
   } else if (LastDef && !PhysRegUse[Reg.id()] &&
              !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
     // Last def defines the super register, add an implicit def of reg.

From 4ac7fcede09d6bd478f9adb95b35e6fb2f3d6335 Mon Sep 17 00:00:00 2001
From: Joey F <jofernau@amd.com>
Date: Sat, 31 May 2025 09:19:48 -0400
Subject: [PATCH 11/12] Fix format and test

---
 llvm/lib/CodeGen/LiveVariables.cpp             | 2 +-
 llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 052400e99b4aa..4ee16238cfa2f 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -253,7 +253,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
     // If LastPartialDef is NULL, it must be using a livein register.
     if (LastPartialDef) {
       LastPartialDef->addOperand(
-        MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
+          MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
     }
   } else if (LastDef && !PhysRegUse[Reg.id()] &&
              !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
diff --git a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
index 87d05e3e2b4b9..66a8b424b5763 100644
--- a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
+++ b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
@@ -5,14 +5,14 @@ define amdgpu_ps <4 x float> @caller(ptr %ptr) {
 ; CHECK-LABEL: caller:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    flat_load_dword v1, v[0:1]
-; CHECK-NEXT:    s_mov_b32 s5, fn@abs32@hi
-; CHECK-NEXT:    s_mov_b32 s4, fn@abs32@lo
-; CHECK-NEXT:    s_mov_b64 s[8:9], 0
 ; CHECK-NEXT:    s_mov_b32 s0, 0
 ; CHECK-NEXT:    s_mov_b32 s1, 0
 ; CHECK-NEXT:    s_mov_b32 s2, 0
-; CHECK-NEXT:    s_mov_b32 s3, 0
+; CHECK-NEXT:    s_mov_b32 s5, fn@abs32@hi
+; CHECK-NEXT:    s_mov_b32 s4, fn@abs32@lo
+; CHECK-NEXT:    s_mov_b64 s[8:9], 0
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    s_mov_b32 s3, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    s_mov_b32 s32, 0
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[4:5]

From 7948dfd2ca531050acf4621fca282b18681502ab Mon Sep 17 00:00:00 2001
From: jofrn <jofernau@amd.com>
Date: Mon, 18 Aug 2025 07:39:50 -0400
Subject: [PATCH 12/12] Update llvm/lib/CodeGen/LiveVariables.cpp

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
---
 llvm/lib/CodeGen/LiveVariables.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 4ee16238cfa2f..b39603ea40166 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -253,7 +253,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
     // If LastPartialDef is NULL, it must be using a livein register.
     if (LastPartialDef) {
       LastPartialDef->addOperand(
-          MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/));
+          MachineOperand::CreateReg(Reg, /*IsDef=*/true, /*IsImp=*/true));
     }
   } else if (LastDef && !PhysRegUse[Reg.id()] &&
              !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))