From d1789c1f4db8cd28c8764f3d31dad89fa3ca74a8 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland@gmail.com>
Date: Tue, 10 Dec 2024 14:46:25 -0800
Subject: [PATCH 1/2] [RISCV][VLOPT] Add getOperandInfo for Vector Store Whole
 Register Instructions

We don't add tests for incompatible LMUL since it would break the type system.
---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp    | 19 ++++++++++++++
 .../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 25 +++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index dabf36480f1dc..de00c06e5caf4 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -247,6 +247,25 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
     llvm_unreachable("Configuration setting instructions do not read or write "
                      "vector registers");
 
+  // Vector Store Whole Register Instructions
+  // EMUL=nr. EEW=eew. Since in-register byte layouts are idential to in-memory
+  // byte layouts, the same data is writen to destination register regardless
+  // of EEW. eew is just a hint to the hardware and has not functional impact.
+  // Therefore, it is be okay if we ignore eew and always use the same EEW to
+  // create more optimization opportunities.
+  // FIXME: Instead of using any SEW, we really should return the SEW in the
+  // instruction and add a field to OperandInfo that says the SEW is just a hint
+  // so that this optimization can use any sew to construct a ratio.
+  case RISCV::VS1R_V:
+    return OperandInfo(RISCVII::VLMUL::LMUL_1, 0);
+  case RISCV::VS2R_V:
+    return OperandInfo(RISCVII::VLMUL::LMUL_2, 0);
+  case RISCV::VS4R_V:
+    return OperandInfo(RISCVII::VLMUL::LMUL_4, 0);
+  case RISCV::VS8R_V:
+    return OperandInfo(RISCVII::VLMUL::LMUL_8, 0);
+
+
   // Vector Integer Arithmetic Instructions
   // Vector Single-Width Integer Add and Subtract
   case RISCV::VADD_VI:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 1071ee5361085..ee953132d2cde 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -483,3 +483,28 @@ body: |
     %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
     %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
 ...
+---
+name: vsNr_v
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsNr_v
+    ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+    ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+    ; CHECK-NEXT: VS1R_V %x, %y
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+    %y:gpr = ADDI $x0, 1
+    VS1R_V %x, %y,
+...
+# FIXME: We can optimize this
+---
+name: vsNr_v_eew
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsNr_v_eew
+    ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+    ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
+    ; CHECK-NEXT: VS1R_V %x, %y
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+    %y:gpr = ADDI $x0, 1
+    VS1R_V %x, %y
+...

From 752e449cdebea0749f3cdef5fb7f2c4597226586 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland@gmail.com>
Date: Wed, 11 Dec 2024 07:45:12 -0800
Subject: [PATCH 2/2] fixup! add incompatible eew test

---
 .../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 22 ++++++++++++-------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index ee953132d2cde..99bf85a3f4163 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -489,11 +489,9 @@ body: |
   bb.0:
     ; CHECK-LABEL: name: vsNr_v
     ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
-    ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
-    ; CHECK-NEXT: VS1R_V %x, %y
+    ; CHECK-NEXT: VS1R_V %x, $noreg
     %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
-    %y:gpr = ADDI $x0, 1
-    VS1R_V %x, %y,
+    VS1R_V %x, $noreg
 ...
 # FIXME: We can optimize this
 ---
@@ -502,9 +500,17 @@ body: |
   bb.0:
     ; CHECK-LABEL: name: vsNr_v_eew
     ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
-    ; CHECK-NEXT: %y:gpr = ADDI $x0, 1
-    ; CHECK-NEXT: VS1R_V %x, %y
+    ; CHECK-NEXT: VS1R_V %x, $noreg
     %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
-    %y:gpr = ADDI $x0, 1
-    VS1R_V %x, %y
+    VS1R_V %x, $noreg
+...
+---
+name: vsNr_v_incompatible_emul
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsNr_v_incompatible_emul
+    ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+    ; CHECK-NEXT: VS1R_V %x, $noreg
+    %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+    VS1R_V %x, $noreg
 ...