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[RISCV][VLOPT] Add getOperandInfo for Vector Store Whole Register Instructions #119570

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[RISCV][VLOPT] Add getOperandInfo for Vector Store Whole Register Instructions #119570

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d1789c1
[RISCV][VLOPT] Add getOperandInfo for Vector Store Whole Register Ins…
michaelmaitland Dec 10, 2024
752e449
fixup! add incompatible eew test
michaelmaitland Dec 11, 2024
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19 changes: 19 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -247,6 +247,25 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
llvm_unreachable("Configuration setting instructions do not read or write "
"vector registers");

// Vector Store Whole Register Instructions
// EMUL=nr. EEW=eew. Since in-register byte layouts are idential to in-memory
// byte layouts, the same data is writen to destination register regardless
// of EEW. eew is just a hint to the hardware and has not functional impact.
// Therefore, it is be okay if we ignore eew and always use the same EEW to
// create more optimization opportunities.
// FIXME: Instead of using any SEW, we really should return the SEW in the
// instruction and add a field to OperandInfo that says the SEW is just a hint
// so that this optimization can use any sew to construct a ratio.
case RISCV::VS1R_V:
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@topperc topperc Dec 11, 2024

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These instructions don't have an SEW or VL operand so I think we would fail this check before we get here

    const MCInstrDesc &Desc = UserMI.getDesc();                                  
    if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags)) {   
      LLVM_DEBUG(dbgs() << "    Abort due to lack of VL or SEW, assume that"     
                           " use VLMAX\n");                                      
      CanReduceVL = false;                                                       
      break;                                                                     
    }

return OperandInfo(RISCVII::VLMUL::LMUL_1, 0);
case RISCV::VS2R_V:
return OperandInfo(RISCVII::VLMUL::LMUL_2, 0);
case RISCV::VS4R_V:
return OperandInfo(RISCVII::VLMUL::LMUL_4, 0);
case RISCV::VS8R_V:
return OperandInfo(RISCVII::VLMUL::LMUL_8, 0);


// Vector Integer Arithmetic Instructions
// Vector Single-Width Integer Add and Subtract
case RISCV::VADD_VI:
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31 changes: 31 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
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Expand Up @@ -483,3 +483,34 @@ body: |
%x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
...
---
name: vsNr_v
body: |
bb.0:
; CHECK-LABEL: name: vsNr_v
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: VS1R_V %x, $noreg
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
VS1R_V %x, $noreg
...
# FIXME: We can optimize this
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@topperc topperc Dec 11, 2024

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What would the optimization be? We didn't optimize the vsNr_v case.

---
name: vsNr_v_eew
body: |
bb.0:
; CHECK-LABEL: name: vsNr_v_eew
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: VS1R_V %x, $noreg
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
VS1R_V %x, $noreg
...
---
name: vsNr_v_incompatible_emul
body: |
bb.0:
; CHECK-LABEL: name: vsNr_v_incompatible_emul
; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: VS1R_V %x, $noreg
%x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
VS1R_V %x, $noreg
...
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