From 2ecc51c1f08b078dce441cfb343464044a139458 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 12 Dec 2024 22:15:21 +0300 Subject: [PATCH 1/6] [TableGen] Allow empty terminator in SequenceToOffsetTable Some clients do not want to emit a terminator after each sub-sequence (they have other means of determining the length of the sub-sequence). This moves `Term` argument from `emit` method to the constructor and makes it optional. It couldn't be made optional while still on the `emit` method because if the terminator wasn't specified, it has to be taken into account in `layout` method as well. The fact that `layout` method was called is now recorded in a dedicated member variable, `IsLaidOut`. `Entries != 0` can no longer be used to reliably check if `layout` method was called because it may be zero for a different reason: the terminator wasn't specified and all added sequences (if any) were empty. This reduces the size of `*LaneMaskLists` and `*SubRegIdxLists` a bit and resolves the removed FIXME. --- llvm/utils/TableGen/AsmWriterEmitter.cpp | 4 +- .../TableGen/Basic/SequenceToOffsetTable.h | 47 ++++++++++++------- llvm/utils/TableGen/DFAEmitter.cpp | 12 ++--- llvm/utils/TableGen/DXILEmitter.cpp | 4 +- llvm/utils/TableGen/InstrInfoEmitter.cpp | 2 +- llvm/utils/TableGen/IntrinsicEmitter.cpp | 2 +- llvm/utils/TableGen/RegisterInfoEmitter.cpp | 29 ++++++------ 7 files changed, 56 insertions(+), 44 deletions(-) diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp index 9880214a37368..64cc80afd0900 100644 --- a/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -338,7 +338,7 @@ void AsmWriterEmitter::EmitGetMnemonic( << "::getMnemonic(const MCInst &MI) const {\n"; // Build an aggregate string, and build a table of offsets into it. - SequenceToOffsetTable StringTable; + SequenceToOffsetTable StringTable(/*Terminator=*/'\0'); /// OpcodeInfo - This encodes the index of the string to use for the first /// chunk of the output as well as indices used for operand printing. @@ -583,7 +583,7 @@ void AsmWriterEmitter::EmitPrintInstruction( static void emitRegisterNameString(raw_ostream &O, StringRef AltName, const std::deque &Registers) { - SequenceToOffsetTable StringTable; + SequenceToOffsetTable StringTable(/*Terminator=*/'\0'); SmallVector AsmNames(Registers.size()); unsigned i = 0; for (const auto &Reg : Registers) { diff --git a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h index 497e74afc18ec..4e1388d3e4528 100644 --- a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h +++ b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h @@ -6,9 +6,8 @@ // //===----------------------------------------------------------------------===// // -// SequenceToOffsetTable can be used to emit a number of null-terminated -// sequences as one big array. Use the same memory when a sequence is a suffix -// of another. +// SequenceToOffsetTable can be used to emit a number of sequences as one big +// array. Uses the same memory when a sequence is a suffix of another. // //===----------------------------------------------------------------------===// @@ -65,8 +64,14 @@ class SequenceToOffsetTable { // Sequences added so far, with suffixes removed. SeqMap Seqs; + // Terminator element to be appended to each added sequence. + std::optional Terminator; + + // True if `layout` method was called. + bool IsLaidOut = false; + // Entries in the final table, or 0 before layout was called. - unsigned Entries; + unsigned Entries = 0; // isSuffix - Returns true if A is a suffix of B. static bool isSuffix(const SeqT &A, const SeqT &B) { @@ -74,12 +79,13 @@ class SequenceToOffsetTable { } public: - SequenceToOffsetTable() : Entries(0) {} + explicit SequenceToOffsetTable(std::optional Terminator) + : Terminator(Terminator) {} /// add - Add a sequence to the table. /// This must be called before layout(). void add(const SeqT &Seq) { - assert(Entries == 0 && "Cannot call add() after layout()"); + assert(!IsLaidOut && "Cannot call add() after layout()"); typename SeqMap::iterator I = Seqs.lower_bound(Seq); // If SeqMap contains a sequence that has Seq as a suffix, I will be @@ -97,25 +103,27 @@ class SequenceToOffsetTable { bool empty() const { return Seqs.empty(); } unsigned size() const { - assert((empty() || Entries) && "Call layout() before size()"); + assert(IsLaidOut && "Call layout() before size()"); return Entries; } /// layout - Computes the final table layout. void layout() { - assert(Entries == 0 && "Can only call layout() once"); + assert(!IsLaidOut && "Can only call layout() once"); + IsLaidOut = true; + // Lay out the table in Seqs iteration order. for (typename SeqMap::iterator I = Seqs.begin(), E = Seqs.end(); I != E; ++I) { I->second = Entries; // Include space for a terminator. - Entries += I->first.size() + 1; + Entries += I->first.size() + Terminator.has_value(); } } /// get - Returns the offset of Seq in the final table. unsigned get(const SeqT &Seq) const { - assert(Entries && "Call layout() before get()"); + assert(IsLaidOut && "Call layout() before get()"); typename SeqMap::const_iterator I = Seqs.lower_bound(Seq); assert(I != Seqs.end() && isSuffix(Seq, I->first) && "get() called with sequence that wasn't added first"); @@ -127,10 +135,10 @@ class SequenceToOffsetTable { /// `\0`. Falls back to emitting a comma-separated integer list if /// `EmitLongStrLiterals` is false void emitStringLiteralDef(raw_ostream &OS, const Twine &Decl) const { - assert(Entries && "Call layout() before emitStringLiteralDef()"); + assert(IsLaidOut && "Call layout() before emitStringLiteralDef()"); if (!EmitLongStrLiterals) { OS << Decl << " = {\n"; - emit(OS, printChar, "0"); + emit(OS, printChar); OS << " 0\n};\n\n"; return; } @@ -143,7 +151,9 @@ class SequenceToOffsetTable { for (const auto &[Seq, Offset] : Seqs) { OS << " /* " << Offset << " */ \""; OS.write_escaped(Seq); - OS << "\\0\"\n"; + if (Terminator) + OS.write_escaped(StringRef(&*Terminator, 1)); + OS << "\"\n"; } OS << "};\n" << "#ifdef __GNUC__\n" @@ -153,16 +163,19 @@ class SequenceToOffsetTable { /// emit - Print out the table as the body of an array initializer. /// Use the Print function to print elements. - void emit(raw_ostream &OS, void (*Print)(raw_ostream &, ElemT), - const char *Term = "0") const { - assert((empty() || Entries) && "Call layout() before emit()"); + void emit(raw_ostream &OS, void (*Print)(raw_ostream &, ElemT)) const { + assert(IsLaidOut && "Call layout() before emit()"); for (const auto &[Seq, Offset] : Seqs) { OS << " /* " << Offset << " */ "; for (const ElemT &Element : Seq) { Print(OS, Element); OS << ", "; } - OS << Term << ",\n"; + if (Terminator) { + Print(OS, *Terminator); + OS << ','; + } + OS << '\n'; } } }; diff --git a/llvm/utils/TableGen/DFAEmitter.cpp b/llvm/utils/TableGen/DFAEmitter.cpp index 264cccf6ac0ca..a42c615879ba7 100644 --- a/llvm/utils/TableGen/DFAEmitter.cpp +++ b/llvm/utils/TableGen/DFAEmitter.cpp @@ -117,19 +117,17 @@ void DfaEmitter::emit(StringRef Name, raw_ostream &OS) { OS << "// transition implies a set of NFA transitions. These are referred\n"; OS << "// to by index in " << Name << "Transitions[].\n"; - SequenceToOffsetTable Table; + SequenceToOffsetTable Table( + /*Terminator=*/std::pair(0, 0)); std::map EmittedIndices; for (auto &T : DfaTransitions) Table.add(T.second.second); Table.layout(); OS << "const std::array " << Name << "TransitionInfo = {{\n"; - Table.emit( - OS, - [](raw_ostream &OS, std::pair P) { - OS << "{" << P.first << ", " << P.second << "}"; - }, - "{0ULL, 0ULL}"); + Table.emit(OS, [](raw_ostream &OS, std::pair P) { + OS << "{" << P.first << ", " << P.second << "}"; + }); OS << "}};\n\n"; diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp index a0c93bed5ad83..b54949ef2dc1a 100644 --- a/llvm/utils/TableGen/DXILEmitter.cpp +++ b/llvm/utils/TableGen/DXILEmitter.cpp @@ -449,8 +449,8 @@ static void emitDXILIntrinsicArgSelectTypes(const RecordKeeper &Records, static void emitDXILOperationTable(ArrayRef Ops, raw_ostream &OS) { // Collect Names. - SequenceToOffsetTable OpClassStrings; - SequenceToOffsetTable OpStrings; + SequenceToOffsetTable OpClassStrings(/*Terminator=*/'\0'); + SequenceToOffsetTable OpStrings(/*Terminator=*/'\0'); StringSet<> ClassSet; for (const auto &Op : Ops) { diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 8c0e27215a736..912a96c40f70e 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -988,7 +988,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OS << "extern const " << TargetName << "InstrTable " << TargetName << "Descs = {\n {\n"; - SequenceToOffsetTable InstrNames; + SequenceToOffsetTable InstrNames(/*Terminator=*/'\0'); unsigned Num = NumberedInstructions.size(); for (const CodeGenInstruction *Inst : reverse(NumberedInstructions)) { // Keep a list of the instruction names. diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp index 093602c3da804..a0ad8e561aa48 100644 --- a/llvm/utils/TableGen/IntrinsicEmitter.cpp +++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp @@ -338,7 +338,7 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints, // If we can compute a 16/32-bit fixed encoding for this intrinsic, do so and // capture it in this vector, otherwise store a ~0U. std::vector FixedEncodings; - SequenceToOffsetTable LongEncodingTable; + SequenceToOffsetTable LongEncodingTable(/*Terminator=*/0); FixedEncodings.reserve(Ints.size()); diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index bfcd52da1c39c..98d752bc07e29 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -288,7 +288,7 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS, << " return PressureLimitTable[Idx];\n" << "}\n\n"; - SequenceToOffsetTable> PSetsSeqs; + SequenceToOffsetTable> PSetsSeqs(/*Terminator=*/-1); // This table may be larger than NumRCs if some register units needed a list // of unit sets that did not correspond to a register class. @@ -309,7 +309,7 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS, OS << "/// Table of pressure sets per register class or unit.\n" << "static const int RCSetsTable[] = {\n"; - PSetsSeqs.emit(OS, printInt, "-1"); + PSetsSeqs.emit(OS, printInt); OS << "};\n\n"; OS << "/// Get the dimensions of register pressure impacted by this " @@ -610,7 +610,7 @@ static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { } static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { - OS << Idx->EnumValue; + OS << (Idx ? Idx->EnumValue : 0); } // Differentially encoded register and regunit lists allow for better @@ -869,22 +869,23 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { typedef std::vector RegVec; // Differentially encoded lists. - SequenceToOffsetTable DiffSeqs; + SequenceToOffsetTable DiffSeqs(/*Terminator=*/0); SmallVector SubRegLists(Regs.size()); SmallVector SuperRegLists(Regs.size()); SmallVector RegUnitLists(Regs.size()); // List of lane masks accompanying register unit sequences. - SequenceToOffsetTable LaneMaskSeqs; + SequenceToOffsetTable LaneMaskSeqs(/*Terminator=*/std::nullopt); SmallVector RegUnitLaneMasks(Regs.size()); // Keep track of sub-register names as well. These are not differentially // encoded. typedef SmallVector SubRegIdxVec; - SequenceToOffsetTable>> SubRegIdxSeqs; + SequenceToOffsetTable>> SubRegIdxSeqs( + /*Terminator=*/std::nullopt); SmallVector SubRegIdxLists(Regs.size()); - SequenceToOffsetTable RegStrings; + SequenceToOffsetTable RegStrings(/*Terminator=*/'\0'); // Precompute register lists for the SequenceToOffsetTable. unsigned i = 0; @@ -936,9 +937,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { // Emit the shared table of regunit lane mask sequences. OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; - // TODO: Omit the terminator since it is never used. The length of this list - // is known implicitly from the corresponding reg unit list. - LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); + LaneMaskSeqs.emit(OS, printMask); OS << "};\n\n"; // Emit the table of sub-register indexes. @@ -994,7 +993,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { // Loop over all of the register classes... emitting each one. OS << "namespace { // Register classes...\n"; - SequenceToOffsetTable RegClassStrings; + SequenceToOffsetTable RegClassStrings(/*Terminator=*/'\0'); // Emit the register enum value arrays for each RegisterClass for (const auto &RC : RegisterClasses) { @@ -1209,7 +1208,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) { unsigned NumModes = CGH.getNumModeIds(); // Build a shared array of value types. - SequenceToOffsetTable> VTSeqs; + SequenceToOffsetTable> VTSeqs( + /*Terminator=*/MVT::Other); for (unsigned M = 0; M < NumModes; ++M) { for (const auto &RC : RegisterClasses) { std::vector S; @@ -1221,7 +1221,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) { } VTSeqs.layout(); OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; - VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); + VTSeqs.emit(OS, printSimpleValueType); OS << "};\n"; // Emit SubRegIndex names, skipping 0. @@ -1307,7 +1307,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) { // Compress the sub-reg index lists. typedef std::vector IdxList; SmallVector SuperRegIdxLists(RegisterClasses.size()); - SequenceToOffsetTable>> SuperRegIdxSeqs; + SequenceToOffsetTable>> SuperRegIdxSeqs( + /*Terminator=*/nullptr); BitVector MaskBV(RegisterClasses.size()); for (const auto &RC : RegisterClasses) { From a3676eda47a65ca50380c717df149bb178779e85 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 13 Dec 2024 00:06:46 +0300 Subject: [PATCH 2/6] Simplify the loop in `layout` --- llvm/utils/TableGen/Basic/SequenceToOffsetTable.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h index 4e1388d3e4528..67cf6677c70b6 100644 --- a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h +++ b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h @@ -116,9 +116,12 @@ class SequenceToOffsetTable { for (typename SeqMap::iterator I = Seqs.begin(), E = Seqs.end(); I != E; ++I) { I->second = Entries; - // Include space for a terminator. - Entries += I->first.size() + Terminator.has_value(); + Entries += I->first.size(); } + + // Include space for terminators. + if (Terminator) + Entries += Seqs.size(); } /// get - Returns the offset of Seq in the final table. From b8294395dee679c03b25d43babded68084db701f Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 13 Dec 2024 00:49:57 +0300 Subject: [PATCH 3/6] Print a dummy element if the array would be empty otherwise --- llvm/utils/TableGen/Basic/SequenceToOffsetTable.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h index 67cf6677c70b6..ccfe746a33377 100644 --- a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h +++ b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h @@ -180,6 +180,13 @@ class SequenceToOffsetTable { } OS << '\n'; } + + // Print a dummy element if the array would be empty otherwise. + if (!Entries) { + OS << " /* dummy */ "; + Print(OS, ElemT()); + OS << '\n'; + } } }; From ba84a60dc875eebc648c759c946f833e3abf0c6a Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 13 Dec 2024 03:37:11 +0300 Subject: [PATCH 4/6] Revert "Simplify the loop in `layout`" This reverts commit a3676eda47a65ca50380c717df149bb178779e85. --- llvm/utils/TableGen/Basic/SequenceToOffsetTable.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h index ccfe746a33377..86313860b3bea 100644 --- a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h +++ b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h @@ -116,12 +116,9 @@ class SequenceToOffsetTable { for (typename SeqMap::iterator I = Seqs.begin(), E = Seqs.end(); I != E; ++I) { I->second = Entries; - Entries += I->first.size(); + // Include space for a terminator. + Entries += I->first.size() + Terminator.has_value(); } - - // Include space for terminators. - if (Terminator) - Entries += Seqs.size(); } /// get - Returns the offset of Seq in the final table. From 8d97f2d3a2704c44f7d11dd3bf1c29b3027671c7 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 13 Dec 2024 03:41:52 +0300 Subject: [PATCH 5/6] Provide a default value for the parameter of the constructor Most of the clients use the default value for the terminator. This reduces change reduces the diff. --- llvm/utils/TableGen/AsmWriterEmitter.cpp | 4 ++-- llvm/utils/TableGen/Basic/SequenceToOffsetTable.h | 2 +- llvm/utils/TableGen/DFAEmitter.cpp | 3 +-- llvm/utils/TableGen/DXILEmitter.cpp | 4 ++-- llvm/utils/TableGen/InstrInfoEmitter.cpp | 2 +- llvm/utils/TableGen/IntrinsicEmitter.cpp | 2 +- llvm/utils/TableGen/RegisterInfoEmitter.cpp | 9 ++++----- 7 files changed, 12 insertions(+), 14 deletions(-) diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp index 64cc80afd0900..9880214a37368 100644 --- a/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -338,7 +338,7 @@ void AsmWriterEmitter::EmitGetMnemonic( << "::getMnemonic(const MCInst &MI) const {\n"; // Build an aggregate string, and build a table of offsets into it. - SequenceToOffsetTable StringTable(/*Terminator=*/'\0'); + SequenceToOffsetTable StringTable; /// OpcodeInfo - This encodes the index of the string to use for the first /// chunk of the output as well as indices used for operand printing. @@ -583,7 +583,7 @@ void AsmWriterEmitter::EmitPrintInstruction( static void emitRegisterNameString(raw_ostream &O, StringRef AltName, const std::deque &Registers) { - SequenceToOffsetTable StringTable(/*Terminator=*/'\0'); + SequenceToOffsetTable StringTable; SmallVector AsmNames(Registers.size()); unsigned i = 0; for (const auto &Reg : Registers) { diff --git a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h index 86313860b3bea..c918365b2289b 100644 --- a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h +++ b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h @@ -79,7 +79,7 @@ class SequenceToOffsetTable { } public: - explicit SequenceToOffsetTable(std::optional Terminator) + explicit SequenceToOffsetTable(std::optional Terminator = ElemT()) : Terminator(Terminator) {} /// add - Add a sequence to the table. diff --git a/llvm/utils/TableGen/DFAEmitter.cpp b/llvm/utils/TableGen/DFAEmitter.cpp index a42c615879ba7..c150620b74175 100644 --- a/llvm/utils/TableGen/DFAEmitter.cpp +++ b/llvm/utils/TableGen/DFAEmitter.cpp @@ -117,8 +117,7 @@ void DfaEmitter::emit(StringRef Name, raw_ostream &OS) { OS << "// transition implies a set of NFA transitions. These are referred\n"; OS << "// to by index in " << Name << "Transitions[].\n"; - SequenceToOffsetTable Table( - /*Terminator=*/std::pair(0, 0)); + SequenceToOffsetTable Table; std::map EmittedIndices; for (auto &T : DfaTransitions) Table.add(T.second.second); diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp index b54949ef2dc1a..a0c93bed5ad83 100644 --- a/llvm/utils/TableGen/DXILEmitter.cpp +++ b/llvm/utils/TableGen/DXILEmitter.cpp @@ -449,8 +449,8 @@ static void emitDXILIntrinsicArgSelectTypes(const RecordKeeper &Records, static void emitDXILOperationTable(ArrayRef Ops, raw_ostream &OS) { // Collect Names. - SequenceToOffsetTable OpClassStrings(/*Terminator=*/'\0'); - SequenceToOffsetTable OpStrings(/*Terminator=*/'\0'); + SequenceToOffsetTable OpClassStrings; + SequenceToOffsetTable OpStrings; StringSet<> ClassSet; for (const auto &Op : Ops) { diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 912a96c40f70e..8c0e27215a736 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -988,7 +988,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OS << "extern const " << TargetName << "InstrTable " << TargetName << "Descs = {\n {\n"; - SequenceToOffsetTable InstrNames(/*Terminator=*/'\0'); + SequenceToOffsetTable InstrNames; unsigned Num = NumberedInstructions.size(); for (const CodeGenInstruction *Inst : reverse(NumberedInstructions)) { // Keep a list of the instruction names. diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp index a0ad8e561aa48..093602c3da804 100644 --- a/llvm/utils/TableGen/IntrinsicEmitter.cpp +++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp @@ -338,7 +338,7 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints, // If we can compute a 16/32-bit fixed encoding for this intrinsic, do so and // capture it in this vector, otherwise store a ~0U. std::vector FixedEncodings; - SequenceToOffsetTable LongEncodingTable(/*Terminator=*/0); + SequenceToOffsetTable LongEncodingTable; FixedEncodings.reserve(Ints.size()); diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index 98d752bc07e29..0c1f5d205ca0f 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -869,7 +869,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { typedef std::vector RegVec; // Differentially encoded lists. - SequenceToOffsetTable DiffSeqs(/*Terminator=*/0); + SequenceToOffsetTable DiffSeqs; SmallVector SubRegLists(Regs.size()); SmallVector SuperRegLists(Regs.size()); SmallVector RegUnitLists(Regs.size()); @@ -885,7 +885,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { /*Terminator=*/std::nullopt); SmallVector SubRegIdxLists(Regs.size()); - SequenceToOffsetTable RegStrings(/*Terminator=*/'\0'); + SequenceToOffsetTable RegStrings; // Precompute register lists for the SequenceToOffsetTable. unsigned i = 0; @@ -993,7 +993,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { // Loop over all of the register classes... emitting each one. OS << "namespace { // Register classes...\n"; - SequenceToOffsetTable RegClassStrings(/*Terminator=*/'\0'); + SequenceToOffsetTable RegClassStrings; // Emit the register enum value arrays for each RegisterClass for (const auto &RC : RegisterClasses) { @@ -1307,8 +1307,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) { // Compress the sub-reg index lists. typedef std::vector IdxList; SmallVector SuperRegIdxLists(RegisterClasses.size()); - SequenceToOffsetTable>> SuperRegIdxSeqs( - /*Terminator=*/nullptr); + SequenceToOffsetTable>> SuperRegIdxSeqs; BitVector MaskBV(RegisterClasses.size()); for (const auto &RC : RegisterClasses) { From 945b0dd92a6c164a9950c690941b1cd418ac4757 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 13 Dec 2024 04:20:31 +0300 Subject: [PATCH 6/6] Fix failing test --- llvm/test/TableGen/MixedCasedMnemonic.td | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/test/TableGen/MixedCasedMnemonic.td b/llvm/test/TableGen/MixedCasedMnemonic.td index 3dc44ab6052c3..cb224ac59c6de 100644 --- a/llvm/test/TableGen/MixedCasedMnemonic.td +++ b/llvm/test/TableGen/MixedCasedMnemonic.td @@ -53,8 +53,8 @@ def :MnemonicAlias<"InstB", "BInst">; // Check that the writer preserves the case of the mnemonics. // WRITER: static const char AsmStrs[] = { -// WRITER: "BInst\0" -// WRITER-NEXT: "aInst\0" +// WRITER: "BInst\000" +// WRITER-NEXT: "aInst\000" // WRITER-NEXT: }; // ALIAS: static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { @@ -73,4 +73,3 @@ def :MnemonicAlias<"InstB", "BInst">; // ALIAS-NEXT case 'b': // 1 string to match. // ALIAS-NEXT Mnemonic = "binst"; // "instb" // ALIAS-NEXT return; -