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[AMDGPU] Assert if stack grows downwards. #119888

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Merged
merged 2 commits into from
Dec 14, 2024
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[AMDGPU] Assert if stack grows downwards. #119888

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assert if stack grows upwards
easyonaadit Dec 13, 2024
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easyonaadit Dec 14, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1181,8 +1181,8 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(

// Guard in case the stack growth direction ever changes with scratch
// instructions.
if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown)
return false;
assert(TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp &&
"Stack grows upwards for AMDGPU\n");

Register Dst = MI.getOperand(0).getReg();
Register AllocSize = MI.getOperand(1).getReg();
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8 changes: 3 additions & 5 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -4041,17 +4041,15 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
Chain = SP.getValue(1);
MaybeAlign Alignment = cast<ConstantSDNode>(Tmp3)->getMaybeAlignValue();
const TargetFrameLowering *TFL = Subtarget->getFrameLowering();
unsigned Opc =
TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp
? ISD::ADD
: ISD::SUB;
assert(TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp &&
"Stack grows upwards for AMDGPU\n");

SDValue ScaledSize = DAG.getNode(
ISD::SHL, dl, VT, Size,
DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));

Align StackAlign = TFL->getStackAlign();
Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
Tmp1 = DAG.getNode(ISD::ADD, dl, VT, SP, ScaledSize); // Value
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@s-barannikov s-barannikov Dec 14, 2024 •
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(not related to this PR, but I thought it was worth reporting)

If I'm reading correctly, the logic is broken for the case when the object alignment is greater than the stack alignment.
The ISD::AND below may result in an address that points below the current SP, possibly into a previously allocated object.

Consider: SP = 40, StackAlign = 8, ScaledSize = 16, (Scaled)Alignment = 32

Tmp1 = ADD 40, 16 = 56
Tmp1 = AND 56, -32 = 32

The new address (32) is less than the previous value of the stack pointer (40).

ADD
And the returned address (Tmp1) points past the allocated object. Probably I don't understand something...

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@easyonaadit easyonaadit Dec 16, 2024

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Hi,
There are 2 things to consider here:

  1. For AMDGPU, the Stack grows upwards (low addr to high addr)
  2. The code here is based on the default implementation, which itself doesn't seem to adjust for a growing up stack.

This patch is actually just a part of fixing the logic flaw you pointed out. There is a fix in progress, you could follow it here:
#119822

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@s-barannikov s-barannikov Dec 16, 2024 •
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The default implementation is dead code for StackGrowsUp. I was going to fix it, but I couldn't add tests for the changes.

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@easyonaadit easyonaadit Dec 18, 2024

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Other than scaling for wave size, the code changes in #119822 serve as a generic implementation for a growing up stack. And there are test cases along with it as well. Could this be replicated?

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@arsenm arsenm Dec 18, 2024

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The only other target that uses positive stack growth is NVPTX

if (Alignment && *Alignment > StackAlign) {
Tmp1 = DAG.getNode(
ISD::AND, dl, VT, Tmp1,
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