release/19.x: [RISCV] Fix typo in CV_SH_rr_inc pattern (#120246) #120296
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@topperc What do you think about merging this PR to the release branch? |
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@llvm/pr-subscribers-backend-risc-v Author: None (llvmbot) ChangesBackport e8ce6c4 Requested by: @topperc Full diff: https://github.com/llvm/llvm-project/pull/120296.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 3bd6da28682863..99485981701479 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -694,7 +694,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
def : CVStriPat<post_store, CV_SW_ri_inc>;
def : CVStrriPat<post_truncsti8, CV_SB_rr_inc>;
- def : CVStrriPat<post_truncsti16, CV_SH_ri_inc>;
+ def : CVStrriPat<post_truncsti16, CV_SH_rr_inc>;
def : CVStrriPat<post_store, CV_SW_rr_inc>;
def : CVStrrPat<truncstorei8, CV_SB_rr>;
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lenary
approved these changes
Dec 17, 2024
This typo in https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td#L701:L701 caused a compiler crash in 'RISC-V Assembly Printer' because CV_SH_ri_inc was selected, leading to `getImmOpValue` being called for a register operand. This bug did not affect the Assembler output and therefore does not trigger any existing unit tests, but is visible by examining the final MIR function. (cherry picked from commit e8ce6c4)
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@topperc (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. |
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Backport e8ce6c4
Requested by: @topperc