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[RISCV][VLOPT] Add vsadd and vsaddu to isSupportedInstr #120358

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[RISCV][VLOPT] Add vsadd and vsaddu to isSupportedInstr #120358

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11 changes: 10 additions & 1 deletion llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -801,6 +801,15 @@ static bool isSupportedInstr(const MachineInstr &MI) {
case RISCV::VMSOF_M:
case RISCV::VIOTA_M:
case RISCV::VID_V:

// Vector Single-Width Saturating Add and Subtract
case RISCV::VSADDU_VI:
case RISCV::VSADDU_VV:
case RISCV::VSADDU_VX:
case RISCV::VSADD_VI:
case RISCV::VSADD_VV:
case RISCV::VSADD_VX:

return true;
}

Expand Down Expand Up @@ -872,7 +881,7 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
const MCInstrDesc &Desc = MI.getDesc();
if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags))
return false;
if (MI.getNumDefs() != 1)
if (MI.getNumExplicitDefs() != 1)
return false;

// If we're not using VLMAX, then we need to be careful whether we are using
Expand Down
120 changes: 120 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
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Expand Up @@ -2925,3 +2925,123 @@ define <vscale x 4 x i32> @vid.v(<vscale x 4 x i32> %c, iXLen %vl) {
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %c, iXLen %vl)
ret <vscale x 4 x i32> %2
}

define <vscale x 4 x i32> @vsaddu_vi(<vscale x 4 x i32> %a, iXLen %vl) {
; NOVLOPT-LABEL: vsaddu_vi:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; NOVLOPT-NEXT: vsaddu.vi v10, v8, 5
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; NOVLOPT-NEXT: vadd.vv v8, v10, v8
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vsaddu_vi:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; VLOPT-NEXT: vsaddu.vi v10, v8, 5
; VLOPT-NEXT: vadd.vv v8, v10, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vsaddu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
ret <vscale x 4 x i32> %2
}

define <vscale x 4 x i32> @vsaddu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
; NOVLOPT-LABEL: vsaddu_vv:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; NOVLOPT-NEXT: vsaddu.vv v8, v8, v10
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; NOVLOPT-NEXT: vadd.vv v8, v8, v10
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vsaddu_vv:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; VLOPT-NEXT: vsaddu.vv v8, v8, v10
; VLOPT-NEXT: vadd.vv v8, v8, v10
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vsaddu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)
ret <vscale x 4 x i32> %2
}

define <vscale x 4 x i32> @vsaddu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
; NOVLOPT-LABEL: vsaddu_vx:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
; NOVLOPT-NEXT: vsaddu.vx v10, v8, a0
; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; NOVLOPT-NEXT: vadd.vv v8, v10, v8
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vsaddu_vx:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; VLOPT-NEXT: vsaddu.vx v10, v8, a0
; VLOPT-NEXT: vadd.vv v8, v10, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vsaddu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
ret <vscale x 4 x i32> %2
}

define <vscale x 4 x i32> @vsadd_vi(<vscale x 4 x i32> %a, iXLen %vl) {
; NOVLOPT-LABEL: vsadd_vi:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; NOVLOPT-NEXT: vsadd.vi v10, v8, 5
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; NOVLOPT-NEXT: vadd.vv v8, v10, v8
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vsadd_vi:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; VLOPT-NEXT: vsadd.vi v10, v8, 5
; VLOPT-NEXT: vadd.vv v8, v10, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vsadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
ret <vscale x 4 x i32> %2
}

define <vscale x 4 x i32> @vsadd_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
; NOVLOPT-LABEL: vsadd_vv:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; NOVLOPT-NEXT: vsadd.vv v8, v8, v10
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; NOVLOPT-NEXT: vadd.vv v8, v8, v10
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vsadd_vv:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; VLOPT-NEXT: vsadd.vv v8, v8, v10
; VLOPT-NEXT: vadd.vv v8, v8, v10
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vsadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)
ret <vscale x 4 x i32> %2
}

define <vscale x 4 x i32> @vsadd_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
; NOVLOPT-LABEL: vsadd_vx:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
; NOVLOPT-NEXT: vsadd.vx v10, v8, a0
; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; NOVLOPT-NEXT: vadd.vv v8, v10, v8
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vsadd_vx:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; VLOPT-NEXT: vsadd.vx v10, v8, a0
; VLOPT-NEXT: vadd.vv v8, v10, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vsadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
ret <vscale x 4 x i32> %2
}
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