diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index e13f41162628a..5e2440c1b57e3 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -310,6 +310,9 @@ class SDUse { /// Get the next SDUse in the use list. SDUse *getNext() const { return Next; } + /// Return the operand # of this use in its user. + inline unsigned getOperandNo() const; + /// Convenience function for get().getNode(). SDNode *getNode() const { return Val.getNode(); } /// Convenience function for get().getResNo(). @@ -824,12 +827,6 @@ END_TWO_BYTE_PACK() } SDUse *operator->() const { return &operator*(); } - - /// Retrieve the operand # of this use in its user. - unsigned getOperandNo() const { - assert(Op && "Cannot dereference end iterator!"); - return (unsigned)(Op - Op->getUser()->OperandList); - } }; class user_iterator { @@ -1303,6 +1300,9 @@ inline void SDValue::dumpr(const SelectionDAG *G) const { } // Define inline functions from the SDUse class. +inline unsigned SDUse::getOperandNo() const { + return this - getUser()->op_begin(); +} inline void SDUse::set(const SDValue &V) { if (Val.getNode()) removeFromList(); diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7a458ff830ab4..6cbfef2d238bb 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -18921,10 +18921,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { SmallVector OtherUses; unsigned MaxSteps = SelectionDAG::getHasPredecessorMaxSteps(); if (isa(Offset)) - for (SDNode::use_iterator UI = BasePtr->use_begin(), - UE = BasePtr->use_end(); - UI != UE; ++UI) { - SDUse &Use = *UI; + for (SDUse &Use : BasePtr->uses()) { // Skip the use that is Ptr and uses of other results from BasePtr's // node (important for nodes that return multiple results). if (Use.getUser() == Ptr.getNode() || Use != BasePtr) @@ -18940,7 +18937,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { break; } - SDValue Op1 = Use.getUser()->getOperand((UI.getOperandNo() + 1) & 1); + SDValue Op1 = Use.getUser()->getOperand((Use.getOperandNo() + 1) & 1); if (!isa(Op1)) { OtherUses.clear(); break; @@ -20931,11 +20928,11 @@ DAGCombiner::getStoreMergeCandidates(StoreSDNode *St, RootCount->second.second > StoreMergeDependenceLimit; }; - auto TryToAddCandidate = [&](SDNode::use_iterator UseIter) { + auto TryToAddCandidate = [&](SDUse &Use) { // This must be a chain use. - if (UseIter.getOperandNo() != 0) + if (Use.getOperandNo() != 0) return; - if (auto *OtherStore = dyn_cast(UseIter->getUser())) { + if (auto *OtherStore = dyn_cast(Use.getUser())) { BaseIndexOffset Ptr; int64_t PtrDiff; if (CandidateMatch(OtherStore, Ptr, PtrDiff) && @@ -20954,19 +20951,19 @@ DAGCombiner::getStoreMergeCandidates(StoreSDNode *St, for (auto I = RootNode->use_begin(), E = RootNode->use_end(); I != E && NumNodesExplored < MaxSearchNodes; ++I, ++NumNodesExplored) { SDNode *User = I->getUser(); - if (I.getOperandNo() == 0 && isa(User)) { // walk down chain - for (auto I2 = User->use_begin(), E2 = User->use_end(); I2 != E2; ++I2) - TryToAddCandidate(I2); + if (I->getOperandNo() == 0 && isa(User)) { // walk down chain + for (SDUse &U2 : User->uses()) + TryToAddCandidate(U2); } // Check stores that depend on the root (e.g. Store 3 in the chart above). - if (I.getOperandNo() == 0 && isa(User)) { - TryToAddCandidate(I); + if (I->getOperandNo() == 0 && isa(User)) { + TryToAddCandidate(*I); } } } else { for (auto I = RootNode->use_begin(), E = RootNode->use_end(); I != E && NumNodesExplored < MaxSearchNodes; ++I, ++NumNodesExplored) - TryToAddCandidate(I); + TryToAddCandidate(*I); } return RootNode; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index ed699e1cc72e3..1abb75eb72b4a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -3755,7 +3755,7 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const { for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end(); Limit < 10 && U != E; ++U, ++Limit) { const TargetRegisterClass *RC = - getOperandRegClass(U->getUser(), U.getOperandNo()); + getOperandRegClass(U->getUser(), U->getOperandNo()); // If the register class is unknown, it could be an unknown // register class that needs to be an SGPR, e.g. an inline asm @@ -3770,7 +3770,7 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const { unsigned Opc = User->getMachineOpcode(); const MCInstrDesc &Desc = SII->get(Opc); if (Desc.isCommutable()) { - unsigned OpIdx = Desc.getNumDefs() + U.getOperandNo(); + unsigned OpIdx = Desc.getNumDefs() + U->getOperandNo(); unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex; if (SII->findCommutedOpIndices(Desc, OpIdx, CommuteIdx1)) { unsigned CommutedOpNo = CommuteIdx1 - Desc.getNumDefs(); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 3423ea1818579..9addeae6a1a4a 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -16874,10 +16874,9 @@ bool SITargetLowering::requiresUniformRegister(MachineFunction &MF, } bool SITargetLowering::hasMemSDNodeUser(SDNode *N) const { - SDNode::use_iterator I = N->use_begin(), E = N->use_end(); - for (; I != E; ++I) { - if (MemSDNode *M = dyn_cast(I->getUser())) { - if (getBasePtrIndex(M) == I.getOperandNo()) + for (SDUse &Use : N->uses()) { + if (MemSDNode *M = dyn_cast(Use.getUser())) { + if (getBasePtrIndex(M) == Use.getOperandNo()) return true; } } diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index d8d3875002125..92df91534fe07 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -16219,13 +16219,12 @@ static SDValue CombineBaseUpdate(SDNode *N, SmallVector BaseUpdates; // Search for a use of the address operand that is an increment. - for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), - UE = Addr.getNode()->use_end(); UI != UE; ++UI) { - SDNode *User = UI->getUser(); - if (UI->getResNo() != Addr.getResNo() || User->getNumOperands() != 2) + for (SDUse &Use : Addr->uses()) { + SDNode *User = Use.getUser(); + if (Use.getResNo() != Addr.getResNo() || User->getNumOperands() != 2) continue; - SDValue Inc = User->getOperand(UI.getOperandNo() == 1 ? 0 : 1); + SDValue Inc = User->getOperand(Use.getOperandNo() == 1 ? 0 : 1); unsigned ConstInc = getPointerConstIncrement(User->getOpcode(), Addr, Inc, DCI.DAG); @@ -16240,15 +16239,14 @@ static SDValue CombineBaseUpdate(SDNode *N, if (findPointerConstIncrement(Addr.getNode(), &Base, &CInc)) { unsigned Offset = getPointerConstIncrement(Addr->getOpcode(), Base, CInc, DCI.DAG); - for (SDNode::use_iterator UI = Base->use_begin(), UE = Base->use_end(); - UI != UE; ++UI) { + for (SDUse &Use : Base->uses()) { - SDNode *User = UI->getUser(); - if (UI->getResNo() != Base.getResNo() || User == Addr.getNode() || + SDNode *User = Use.getUser(); + if (Use.getResNo() != Base.getResNo() || User == Addr.getNode() || User->getNumOperands() != 2) continue; - SDValue UserInc = User->getOperand(UI.getOperandNo() == 0 ? 1 : 0); + SDValue UserInc = User->getOperand(Use.getOperandNo() == 0 ? 1 : 0); unsigned UserOffset = getPointerConstIncrement(User->getOpcode(), Base, UserInc, DCI.DAG); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 43ca5456ee3e2..10db4f552cdcf 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1302,8 +1302,8 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector &&Nodes) { EVT OpVT = OpI1.getValueType(); if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1) continue; - for (auto I = N->use_begin(), E = N->use_end(); I != E; ++I) { - SDNode *U = I->getUser(); + for (SDUse &Use : N->uses()) { + SDNode *U = Use.getUser(); if (U->getNumValues() != 1) continue; EVT UVT = U->getValueType(0); @@ -1316,7 +1316,7 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector &&Nodes) { continue; // Potentially simplifiable operation. - unsigned I1N = I.getOperandNo(); + unsigned I1N = Use.getOperandNo(); SmallVector Ops(U->getNumOperands()); for (unsigned i = 0, n = U->getNumOperands(); i != n; ++i) Ops[i] = U->getOperand(i); diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp index 79f5ec3ca5572..4297325cf0e64 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.cpp +++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp @@ -1849,10 +1849,10 @@ static bool hasNonFlagsUse(SDValue Op) { for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE; ++UI) { SDNode *User = UI->getUser(); - unsigned UOpNo = UI.getOperandNo(); + unsigned UOpNo = UI->getOperandNo(); if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { - // Look pass truncate. - UOpNo = User->use_begin().getOperandNo(); + // Look past truncate. + UOpNo = User->use_begin()->getOperandNo(); User = User->use_begin()->getUser(); } diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 4fe8383557b32..2e0ee59d901b8 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -954,9 +954,8 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) { // Cannot use range-based for loop here as we need the actual use (i.e. we // need the operand number corresponding to the use). A range-based for // will unbox the use and provide an SDNode*. - for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); UI != UE; - ++UI) { - SDNode *User = UI->getUser(); + for (SDUse &Use : N->uses()) { + SDNode *User = Use.getUser(); unsigned Opc = User->isMachineOpcode() ? User->getMachineOpcode() : User->getOpcode(); switch (Opc) { @@ -972,7 +971,7 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) { return 0; StoreSDNode *STN = cast(User); unsigned MemVTSize = STN->getMemoryVT().getSizeInBits(); - if (MemVTSize == 64 || UI.getOperandNo() != 0) + if (MemVTSize == 64 || Use.getOperandNo() != 0) return 0; MaxTruncation = std::max(MaxTruncation, MemVTSize); continue; @@ -981,7 +980,7 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) { case PPC::STWX8: case PPC::STWU8: case PPC::STWUX8: - if (UI.getOperandNo() != 0) + if (Use.getOperandNo() != 0) return 0; MaxTruncation = std::max(MaxTruncation, 32u); continue; @@ -989,7 +988,7 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) { case PPC::STHX8: case PPC::STHU8: case PPC::STHUX8: - if (UI.getOperandNo() != 0) + if (Use.getOperandNo() != 0) return 0; MaxTruncation = std::max(MaxTruncation, 16u); continue; @@ -997,7 +996,7 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) { case PPC::STBX8: case PPC::STBU8: case PPC::STBUX8: - if (UI.getOperandNo() != 0) + if (Use.getOperandNo() != 0) return 0; MaxTruncation = std::max(MaxTruncation, 8u); continue; diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index dc45108e55e20..fa3357f3eacc3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -3293,8 +3293,8 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits, if (Depth == 0 && !Node->getValueType(0).isScalarInteger()) return false; - for (auto UI = Node->use_begin(), UE = Node->use_end(); UI != UE; ++UI) { - SDNode *User = UI->getUser(); + for (SDUse &Use : Node->uses()) { + SDNode *User = Use.getUser(); // Users of this node should have already been instruction selected if (!User->isMachineOpcode()) return false; @@ -3302,7 +3302,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits, // TODO: Add more opcodes? switch (User->getMachineOpcode()) { default: - if (vectorPseudoHasAllNBitUsers(User, UI.getOperandNo(), Bits, TII)) + if (vectorPseudoHasAllNBitUsers(User, Use.getOperandNo(), Bits, TII)) break; return false; case RISCV::ADDW: @@ -3353,7 +3353,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits, case RISCV::BCLR: case RISCV::BINV: // Shift amount operands only use log2(Xlen) bits. - if (UI.getOperandNo() == 1 && Bits >= Log2_32(Subtarget->getXLen())) + if (Use.getOperandNo() == 1 && Bits >= Log2_32(Subtarget->getXLen())) break; return false; case RISCV::SLLI: @@ -3417,19 +3417,19 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits, case RISCV::SH3ADD_UW: // The first operand to add.uw/shXadd.uw is implicitly zero extended from // 32 bits. - if (UI.getOperandNo() == 0 && Bits >= 32) + if (Use.getOperandNo() == 0 && Bits >= 32) break; return false; case RISCV::SB: - if (UI.getOperandNo() == 0 && Bits >= 8) + if (Use.getOperandNo() == 0 && Bits >= 8) break; return false; case RISCV::SH: - if (UI.getOperandNo() == 0 && Bits >= 16) + if (Use.getOperandNo() == 0 && Bits >= 16) break; return false; case RISCV::SW: - if (UI.getOperandNo() == 0 && Bits >= 32) + if (Use.getOperandNo() == 0 && Bits >= 32) break; return false; } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 01ef101ff8947..ea8814aa2b4fc 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -15688,14 +15688,12 @@ static SDValue combineOp_VLToVWOp_VL(SDNode *N, auto AppendUsersIfNeeded = [&Worklist, &Subtarget, &Inserted](const NodeExtensionHelper &Op) { if (Op.needToPromoteOtherUsers()) { - for (SDNode::use_iterator UI = Op.OrigOperand->use_begin(), - UE = Op.OrigOperand->use_end(); - UI != UE; ++UI) { - SDNode *TheUser = UI->getUser(); + for (SDUse &Use : Op.OrigOperand->uses()) { + SDNode *TheUser = Use.getUser(); if (!NodeExtensionHelper::isSupportedRoot(TheUser, Subtarget)) return false; // We only support the first 2 operands of FMA. - if (UI.getOperandNo() >= 2) + if (Use.getOperandNo() >= 2) return false; if (Inserted.insert(TheUser).second) Worklist.push_back(TheUser); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 826735d97226a..2528ca553d3e9 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -22868,13 +22868,12 @@ static SDValue MatchVectorAllEqualTest(SDValue LHS, SDValue RHS, /// return true if \c Op has a use that doesn't just read flags. static bool hasNonFlagsUse(SDValue Op) { - for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE; - ++UI) { - SDNode *User = UI->getUser(); - unsigned UOpNo = UI.getOperandNo(); + for (SDUse &Use : Op->uses()) { + SDNode *User = Use.getUser(); + unsigned UOpNo = Use.getOperandNo(); if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { // Look past truncate. - UOpNo = User->use_begin().getOperandNo(); + UOpNo = User->use_begin()->getOperandNo(); User = User->use_begin()->getUser(); } @@ -46721,11 +46720,10 @@ static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG, return SDValue(); auto OnlyUsedAsSelectCond = [](SDValue Cond) { - for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end(); - UI != UE; ++UI) - if ((UI->getUser()->getOpcode() != ISD::VSELECT && - UI->getUser()->getOpcode() != X86ISD::BLENDV) || - UI.getOperandNo() != 0) + for (SDUse &Use : Cond->uses()) + if ((Use.getUser()->getOpcode() != ISD::VSELECT && + Use.getUser()->getOpcode() != X86ISD::BLENDV) || + Use.getOperandNo() != 0) return false; return true;