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Merged
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Dec 23, 2024
Merged

[AMDGPU] Add some more GFX12 test coverage #120581

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7801f98
[AMDGPU] Add some more GFX12 test coverage
jayfoad Dec 19, 2024
8b0f05b
Use named values
jayfoad Dec 20, 2024
5800790
Remove redundant test
jayfoad Dec 20, 2024
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567 changes: 567 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1150 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1150 %s

---
name: sitofp_i32_to_f32
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
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@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1150 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1150 %s

---
name: fadd_f32
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir
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@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1150 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1150 %s

---
name: f32_olt
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168 changes: 168 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
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@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s

define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
; GFX11-LABEL: v_interp_f32:
Expand All @@ -21,6 +23,25 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m
; GFX11-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7
; GFX11-NEXT: exp mrt0 v3, v2, v5, v4 done
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: v_interp_f32:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_mov_b32 s3, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12-NEXT: s_mov_b32 m0, s2
; GFX12-NEXT: ds_param_load v0, attr0.y wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: ds_param_load v1, attr1.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: s_mov_b32 exec_lo, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: v_mov_b32_e32 v4, s1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_interp_p10_f32 v3, v0, v2, v0 wait_exp:1
; GFX12-NEXT: v_interp_p10_f32 v2, v1, v2, v1 wait_exp:0
; GFX12-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7
; GFX12-NEXT: export mrt0 v3, v2, v5, v4 done
; GFX12-NEXT: s_endpgm
main_body:
%p0 = call float @llvm.amdgcn.lds.param.load(i32 1, i32 0, i32 %m0)
%p1 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 1, i32 %m0)
Expand Down Expand Up @@ -57,6 +78,31 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr
; GFX11-NEXT: v_interp_p2_f32 v4, v3, v5, v4 wait_exp:7
; GFX11-NEXT: exp mrt0 v6, v7, v8, v4 done
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: v_interp_f32_many:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_mov_b32 s3, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12-NEXT: s_mov_b32 m0, s2
; GFX12-NEXT: ds_param_load v0, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: ds_param_load v1, attr1.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: ds_param_load v2, attr2.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: ds_param_load v3, attr3.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: s_mov_b32 exec_lo, s3
; GFX12-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_interp_p10_f32 v6, v0, v4, v0 wait_exp:3
; GFX12-NEXT: v_interp_p10_f32 v7, v1, v4, v1 wait_exp:2
; GFX12-NEXT: v_interp_p10_f32 v8, v2, v4, v2 wait_exp:1
; GFX12-NEXT: v_interp_p10_f32 v4, v3, v4, v3 wait_exp:0
; GFX12-NEXT: v_interp_p2_f32 v6, v0, v5, v6 wait_exp:7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_interp_p2_f32 v7, v1, v5, v7 wait_exp:7
; GFX12-NEXT: v_interp_p2_f32 v8, v2, v5, v8 wait_exp:7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-NEXT: v_interp_p2_f32 v4, v3, v5, v4 wait_exp:7
; GFX12-NEXT: export mrt0 v6, v7, v8, v4 done
; GFX12-NEXT: s_endpgm
main_body:
%p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)
%p1 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 1, i32 %m0)
Expand Down Expand Up @@ -99,6 +145,31 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0
; GFX11-NEXT: v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7
; GFX11-NEXT: exp mrt0 v6, v7, v8, v0 done
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: v_interp_f32_many_vm:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off offset:4
; GFX12-NEXT: s_mov_b32 m0, s0
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12-NEXT: ds_param_load v2, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: ds_param_load v3, attr1.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: ds_param_load v4, attr2.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: ds_param_load v5, attr3.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_interp_p10_f32 v6, v2, v0, v2 wait_exp:3
; GFX12-NEXT: v_interp_p10_f32 v7, v3, v0, v3 wait_exp:2
; GFX12-NEXT: v_interp_p10_f32 v8, v4, v0, v4 wait_exp:1
; GFX12-NEXT: v_interp_p10_f32 v0, v5, v0, v5 wait_exp:0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_interp_p2_f32 v6, v2, v1, v6 wait_exp:7
; GFX12-NEXT: v_interp_p2_f32 v7, v3, v1, v7 wait_exp:7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_interp_p2_f32 v8, v4, v1, v8 wait_exp:7
; GFX12-NEXT: v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7
; GFX12-NEXT: export mrt0 v6, v7, v8, v0 done
; GFX12-NEXT: s_endpgm
main_body:
%i.ptr = getelementptr float, ptr addrspace(1) %ptr, i32 1
%i = load float, ptr addrspace(1) %i.ptr, align 4
Expand Down Expand Up @@ -156,6 +227,42 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
; GFX11-FAKE16-NEXT: v_interp_p2_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: v_interp_f16:
; GFX12-TRUE16: ; %bb.0: ; %main_body
; GFX12-TRUE16-NEXT: s_mov_b32 s3, exec_lo
; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12-TRUE16-NEXT: s_mov_b32 m0, s2
; GFX12-TRUE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: v_interp_f16:
; GFX12-FAKE16: ; %bb.0: ; %main_body
; GFX12-FAKE16-NEXT: s_mov_b32 s3, exec_lo
; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12-FAKE16-NEXT: s_mov_b32 m0, s2
; GFX12-FAKE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0
; GFX12-FAKE16-NEXT: v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
; GFX12-FAKE16-NEXT: v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_interp_p2_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0
; GFX12-FAKE16-NEXT: ; return to shader part epilog
main_body:
%p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)
%l_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float %p0, float %i, float %p0, i1 0)
Expand Down Expand Up @@ -202,6 +309,42 @@ define amdgpu_ps half @v_interp_rtz_f16(float inreg %i, float inreg %j, i32 inre
; GFX11-FAKE16-NEXT: v_interp_p2_rtz_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: v_interp_rtz_f16:
; GFX12-TRUE16: ; %bb.0: ; %main_body
; GFX12-TRUE16-NEXT: s_mov_b32 s3, exec_lo
; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12-TRUE16-NEXT: s_mov_b32 m0, s2
; GFX12-TRUE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
; GFX12-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
; GFX12-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: v_interp_rtz_f16:
; GFX12-FAKE16: ; %bb.0: ; %main_body
; GFX12-FAKE16-NEXT: s_mov_b32 s3, exec_lo
; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12-FAKE16-NEXT: s_mov_b32 m0, s2
; GFX12-FAKE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
; GFX12-FAKE16-NEXT: s_mov_b32 exec_lo, s3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_interp_p10_rtz_f16_f32 v3, v1, v0, v1 wait_exp:0
; GFX12-FAKE16-NEXT: v_interp_p10_rtz_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
; GFX12-FAKE16-NEXT: v_interp_p2_rtz_f16_f32 v3, v1, v2, v3 wait_exp:7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_interp_p2_rtz_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0
; GFX12-FAKE16-NEXT: ; return to shader part epilog
main_body:
%p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)
%l_p0 = call float @llvm.amdgcn.interp.p10.rtz.f16(float %p0, float %i, float %p0, i1 0)
Expand Down Expand Up @@ -237,6 +380,31 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: v_interp_f16_imm_params:
; GFX12-TRUE16: ; %bb.0: ; %main_body
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, 0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v2 wait_exp:7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: v_interp_f16_imm_params:
; GFX12-FAKE16: ; %bb.0: ; %main_body
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_interp_p10_f16_f32 v1, v0, v1, v0 wait_exp:7
; GFX12-FAKE16-NEXT: v_interp_p2_f16_f32 v0, v0, v2, v0 wait_exp:7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v1, v0
; GFX12-FAKE16-NEXT: ; return to shader part epilog
main_body:
%l_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float 0.0, float %i, float 0.0, i1 0)
%l_p1 = call half @llvm.amdgcn.interp.inreg.p2.f16(float 0.0, float %j, float 0.0, i1 0)
Expand Down
66 changes: 66 additions & 0 deletions llvm/test/CodeGen/AMDGPU/fmaximum3.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3766,3 +3766,69 @@ define <2 x double> @v_no_fmaximum3_f64__multi_use(double %a, double %b, double
%insert.1 = insertelement <2 x double> %insert.0, double %max1, i32 1
ret <2 x double> %insert.1
}

; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of maximum3
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@arsenm arsenm Dec 20, 2024

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This is achieved by v_fmaximum3_v2f16 already? This one just has a second instance

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@jayfoad jayfoad Dec 20, 2024

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Good point. This had been removed upstream but for some reason lived on in our downstream branch.

; since there are no pack instructions for fmaximum3.
define <2 x half> @no_fmaximum3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) {
; GFX12-LABEL: no_fmaximum3_v2f16:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_pk_maximum_f16 v0, v2, v0
; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX940-LABEL: no_fmaximum3_v2f16:
; GFX940: ; %bb.0: ; %entry
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT: v_pk_max_f16 v4, v0, v1
; GFX940-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX940-NEXT: s_mov_b32 s0, 0x5040100
; GFX940-NEXT: s_nop 0
; GFX940-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc
; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX940-NEXT: s_nop 1
; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX940-NEXT: v_perm_b32 v1, v0, v6, s0
; GFX940-NEXT: v_pk_max_f16 v1, v2, v1
; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v6
; GFX940-NEXT: s_nop 1
; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v2, v0 src0_sel:WORD_1 src1_sel:DWORD
; GFX940-NEXT: s_nop 1
; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
; GFX940-NEXT: v_perm_b32 v1, v0, v4, s0
; GFX940-NEXT: v_pk_max_f16 v1, v1, v3
; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v4, v3
; GFX940-NEXT: s_nop 1
; GFX940-NEXT: v_cndmask_b32_e32 v2, v5, v1, vcc
; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v3 src0_sel:DWORD src1_sel:WORD_1
; GFX940-NEXT: s_nop 1
; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
; GFX940-NEXT: v_perm_b32 v0, v0, v2, s0
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: no_fmaximum3_v2f16:
; GFX950: ; %bb.0: ; %entry
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_pk_maximum3_f16 v0, v0, v1, v1
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_pk_maximum3_f16 v0, v2, v0, v0
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_pk_maximum3_f16 v0, v0, v3, v3
; GFX950-NEXT: s_setpc_b64 s[30:31]
entry:
%max = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
%max1 = call <2 x half> @llvm.maximum.v2f16(<2 x half> %c, <2 x half> %max)
%res = call <2 x half> @llvm.maximum.v2f16(<2 x half> %max1, <2 x half> %d)
ret <2 x half> %res
}
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