From 86c55df5204cd2ca26566e38e263cc4cbabeee72 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Fri, 20 Dec 2024 15:18:15 +0800 Subject: [PATCH 1/3] [CodeGen] Add MachineRegisterClassInfo analysis pass Which is a wrapper of `RegisterClassInfo`. This can cache the result of `RegisterClassInfo` and hence we can reduce compile time. --- llvm/include/llvm/CodeGen/MachinePipeliner.h | 2 +- .../llvm/CodeGen/MachineRegisterClassInfo.h | 57 +++++++++++++++++++ llvm/include/llvm/CodeGen/MachineScheduler.h | 6 -- llvm/include/llvm/InitializePasses.h | 1 + .../llvm/Passes/MachinePassRegistry.def | 2 + llvm/lib/CodeGen/BreakFalseDeps.cpp | 13 +++-- llvm/lib/CodeGen/CMakeLists.txt | 1 + llvm/lib/CodeGen/MachineCombiner.cpp | 10 +++- llvm/lib/CodeGen/MachinePipeliner.cpp | 11 +++- llvm/lib/CodeGen/MachineRegisterClassInfo.cpp | 46 +++++++++++++++ llvm/lib/CodeGen/MachineScheduler.cpp | 23 ++++---- llvm/lib/CodeGen/MachineSink.cpp | 24 +++++--- llvm/lib/CodeGen/PostRASchedulerList.cpp | 28 ++++++--- llvm/lib/CodeGen/RegisterCoalescer.cpp | 23 +++++--- llvm/lib/CodeGen/ShrinkWrap.cpp | 9 ++- llvm/lib/Passes/PassBuilder.cpp | 1 + .../AArch64/AArch64A57FPLoadBalancing.cpp | 11 +++- .../Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 18 +++--- llvm/test/CodeGen/AArch64/O3-pipeline.ll | 4 ++ llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 17 ++++++ .../CodeGen/AMDGPU/sgpr-regalloc-flags.ll | 5 ++ llvm/test/CodeGen/ARM/O3-pipeline.ll | 5 ++ llvm/test/CodeGen/LoongArch/opt-pipeline.ll | 4 ++ llvm/test/CodeGen/PowerPC/O3-pipeline.ll | 5 ++ llvm/test/CodeGen/RISCV/O3-pipeline.ll | 3 + llvm/test/CodeGen/X86/opt-pipeline.ll | 6 ++ 26 files changed, 267 insertions(+), 68 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h create mode 100644 llvm/lib/CodeGen/MachineRegisterClassInfo.cpp diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h index 120b559c20305..b486af4d03307 100644 --- a/llvm/include/llvm/CodeGen/MachinePipeliner.h +++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h @@ -74,7 +74,7 @@ class MachinePipeliner : public MachineFunctionPass { const MachineDominatorTree *MDT = nullptr; const InstrItineraryData *InstrItins = nullptr; const TargetInstrInfo *TII = nullptr; - RegisterClassInfo RegClassInfo; + RegisterClassInfo *RegClassInfo = nullptr; bool disabledByPragma = false; unsigned II_setByPragma = 0; diff --git a/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h new file mode 100644 index 0000000000000..dd8e34cab0bdd --- /dev/null +++ b/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h @@ -0,0 +1,57 @@ +//=- MachineRegisterClassInfo.h - Machine Register Class Info -----*- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This analysis calculates register class info via RegisterClassInfo. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H +#define LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H + +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachinePassManager.h" +#include "llvm/CodeGen/RegisterClassInfo.h" +#include "llvm/Pass.h" + +namespace llvm { + +class MachineRegisterClassInfoAnalysis + : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + + static AnalysisKey Key; + +public: + using Result = RegisterClassInfo; + + Result run(MachineFunction &, MachineFunctionAnalysisManager &); +}; + +class MachineRegisterClassInfoWrapperPass : public MachineFunctionPass { + virtual void anchor(); + + RegisterClassInfo RCI; + +public: + static char ID; + + MachineRegisterClassInfoWrapperPass(); + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + RegisterClassInfo &getRCI() { return RCI; } + const RegisterClassInfo &getRCI() const { return RCI; } +}; +} // namespace llvm + +#endif diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h index bc00d0b4ff852..99ed485645e5f 100644 --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -146,13 +146,7 @@ struct MachineSchedContext { const TargetMachine *TM = nullptr; AAResults *AA = nullptr; LiveIntervals *LIS = nullptr; - RegisterClassInfo *RegClassInfo; - - MachineSchedContext(); - MachineSchedContext &operator=(const MachineSchedContext &other) = delete; - MachineSchedContext(const MachineSchedContext &other) = delete; - virtual ~MachineSchedContext(); }; /// MachineSchedRegistry provides a selection of available machine instruction diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 460c7eb3ebe24..3edf75e26efce 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -206,6 +206,7 @@ void initializeMachineOutlinerPass(PassRegistry &); void initializeMachinePipelinerPass(PassRegistry &); void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &); void initializeMachineRegionInfoPassPass(PassRegistry &); +void initializeMachineRegisterClassInfoWrapperPassPass(PassRegistry &); void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &); void initializeMachineSchedulerLegacyPass(PassRegistry &); void initializeMachineSinkingLegacyPass(PassRegistry &); diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index d3320ef82098c..ebbaf36d02f70 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -113,6 +113,8 @@ MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter", MachineOptimizationRemarkEmitterAnalysis()) MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree", MachinePostDominatorTreeAnalysis()) +MACHINE_FUNCTION_ANALYSIS("machine-reg-class-info", + MachineRegisterClassInfoAnalysis()) MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis()) MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) MACHINE_FUNCTION_ANALYSIS("regalloc-evict", RegAllocEvictionAdvisorAnalysis()) diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp index 618e41894b29b..6d80e82beafa4 100644 --- a/llvm/lib/CodeGen/BreakFalseDeps.cpp +++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp @@ -20,6 +20,7 @@ #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/ReachingDefAnalysis.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/TargetInstrInfo.h" @@ -38,7 +39,7 @@ class BreakFalseDeps : public MachineFunctionPass { MachineFunction *MF = nullptr; const TargetInstrInfo *TII = nullptr; const TargetRegisterInfo *TRI = nullptr; - RegisterClassInfo RegClassInfo; + RegisterClassInfo *RegClassInfo = nullptr; /// List of undefined register reads in this block in forward order. std::vector> UndefReads; @@ -57,6 +58,7 @@ class BreakFalseDeps : public MachineFunctionPass { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); + AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -101,7 +103,9 @@ class BreakFalseDeps : public MachineFunctionPass { #define DEBUG_TYPE "break-false-deps" char BreakFalseDeps::ID = 0; -INITIALIZE_PASS_BEGIN(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false) +INITIALIZE_PASS_BEGIN(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, + false) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis) INITIALIZE_PASS_END(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false) @@ -153,7 +157,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, // max clearance or clearance higher than Pref. unsigned MaxClearance = 0; unsigned MaxClearanceReg = OriginalReg; - ArrayRef Order = RegClassInfo.getOrder(OpRC); + ArrayRef Order = RegClassInfo->getOrder(OpRC); for (MCPhysReg Reg : Order) { unsigned Clearance = RDA->getClearance(MI, Reg); if (Clearance <= MaxClearance) @@ -285,8 +289,7 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) { TII = MF->getSubtarget().getInstrInfo(); TRI = MF->getSubtarget().getRegisterInfo(); RDA = &getAnalysis(); - - RegClassInfo.runOnMachineFunction(mf); + RegClassInfo = &getAnalysis().getRCI(); LLVM_DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n"); diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt index 0e237ba31a8ca..4b2640325a360 100644 --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -142,6 +142,7 @@ add_llvm_component_library(LLVMCodeGen MachinePipeliner.cpp MachinePostDominators.cpp MachineRegionInfo.cpp + MachineRegisterClassInfo.cpp MachineRegisterInfo.cpp MachineScheduler.cpp MachineSink.cpp diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp index 54e2a009b464d..483890412e4f4 100644 --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -19,6 +19,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineSizeOpts.h" #include "llvm/CodeGen/MachineTraceMetrics.h" @@ -73,7 +74,7 @@ class MachineCombiner : public MachineFunctionPass { MachineTraceMetrics::Ensemble *TraceEnsemble = nullptr; MachineBlockFrequencyInfo *MBFI = nullptr; ProfileSummaryInfo *PSI = nullptr; - RegisterClassInfo RegClassInfo; + RegisterClassInfo *RegClassInfo = nullptr; TargetSchedModel TSchedModel; @@ -130,6 +131,7 @@ char &llvm::MachineCombinerID = MachineCombiner::ID; INITIALIZE_PASS_BEGIN(MachineCombiner, DEBUG_TYPE, "Machine InstCombiner", false, false) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineTraceMetricsWrapperPass) INITIALIZE_PASS_END(MachineCombiner, DEBUG_TYPE, "Machine InstCombiner", false, false) @@ -139,6 +141,8 @@ void MachineCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); AU.addRequired(); AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -571,7 +575,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) { bool OptForSize = llvm::shouldOptimizeForSize(MBB, PSI, MBFI); bool DoRegPressureReduce = - TII->shouldReduceRegisterPressure(MBB, &RegClassInfo); + TII->shouldReduceRegisterPressure(MBB, RegClassInfo); while (BlockIter != MBB->end()) { auto &MI = *BlockIter++; @@ -730,7 +734,7 @@ bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) { &getAnalysis().getBFI() : nullptr; TraceEnsemble = nullptr; - RegClassInfo.runOnMachineFunction(MF); + RegClassInfo = &getAnalysis().getRCI(); LLVM_DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n'); if (!TII->useMachineCombiner()) { diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 19e8b44b69b01..534f932ce6624 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -58,6 +58,7 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ModuloSchedule.h" #include "llvm/CodeGen/Register.h" @@ -234,6 +235,7 @@ INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_END(MachinePipeliner, DEBUG_TYPE, "Modulo Software Pipelining", false, false) @@ -263,8 +265,8 @@ bool MachinePipeliner::runOnMachineFunction(MachineFunction &mf) { MLI = &getAnalysis().getLI(); MDT = &getAnalysis().getDomTree(); ORE = &getAnalysis().getORE(); + RegClassInfo = &getAnalysis().getRCI(); TII = MF->getSubtarget().getInstrInfo(); - RegClassInfo.runOnMachineFunction(*MF); for (const auto &L : *MLI) scheduleLoop(*L); @@ -471,7 +473,7 @@ bool MachinePipeliner::swingModuloScheduler(MachineLoop &L) { assert(L.getBlocks().size() == 1 && "SMS works on single blocks only."); SwingSchedulerDAG SMS( - *this, L, getAnalysis().getLIS(), RegClassInfo, + *this, L, getAnalysis().getLIS(), *RegClassInfo, II_setByPragma, LI.LoopPipelinerInfo.get()); MachineBasicBlock *MBB = L.getHeader(); @@ -502,6 +504,8 @@ void MachinePipeliner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addRequired(); AU.addRequired(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -514,7 +518,8 @@ bool MachinePipeliner::runWindowScheduler(MachineLoop &L) { Context.TM = &getAnalysis().getTM(); Context.AA = &getAnalysis().getAAResults(); Context.LIS = &getAnalysis().getLIS(); - Context.RegClassInfo->runOnMachineFunction(*MF); + Context.RegClassInfo = + &getAnalysis().getRCI(); WindowScheduler WS(&Context, L); return WS.run(); } diff --git a/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp b/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp new file mode 100644 index 0000000000000..953de35068c16 --- /dev/null +++ b/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp @@ -0,0 +1,46 @@ +//===- MachineRegisterClassInfo.cpp - Machine Register Class Info ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This analysis calculates register class info via RegisterClassInfo. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/MachineRegisterClassInfo.h" +#include "llvm/CodeGen/RegisterClassInfo.h" +#include "llvm/InitializePasses.h" + +using namespace llvm; + +INITIALIZE_PASS(MachineRegisterClassInfoWrapperPass, "machine-reg-class-info", + "Machine Register Class Info Analysis", true, true) + +MachineRegisterClassInfoAnalysis::Result +MachineRegisterClassInfoAnalysis::run(MachineFunction &MF, + MachineFunctionAnalysisManager &) { + RegisterClassInfo RCI; + RCI.runOnMachineFunction(MF); + return RCI; +} + +char MachineRegisterClassInfoWrapperPass::ID = 0; + +MachineRegisterClassInfoWrapperPass::MachineRegisterClassInfoWrapperPass() + : MachineFunctionPass(ID), RCI() { + PassRegistry &Registry = *PassRegistry::getPassRegistry(); + initializeMachineRegisterClassInfoWrapperPassPass(Registry); +} + +bool MachineRegisterClassInfoWrapperPass::runOnMachineFunction( + MachineFunction &MF) { + RCI.runOnMachineFunction(MF); + return false; +} + +void MachineRegisterClassInfoWrapperPass::anchor() {} + +AnalysisKey MachineRegisterClassInfoAnalysis::Key; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 5086ee8829b25..4553648f7933e 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -31,6 +31,7 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachinePassRegistry.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterPressure.h" @@ -206,14 +207,6 @@ void ScheduleDAGMutation::anchor() {} // Machine Instruction Scheduling Pass and Registry //===----------------------------------------------------------------------===// -MachineSchedContext::MachineSchedContext() { - RegClassInfo = new RegisterClassInfo(); -} - -MachineSchedContext::~MachineSchedContext() { - delete RegClassInfo; -} - namespace llvm { namespace impl_detail { @@ -236,6 +229,7 @@ class MachineSchedulerImpl : public MachineSchedulerBase { MachineDominatorTree &MDT; AAResults &AA; LiveIntervals &LIS; + RegisterClassInfo &RegClassInfo; }; MachineSchedulerImpl() {} @@ -336,6 +330,8 @@ void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); AU.addRequired(); AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -348,6 +344,7 @@ INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched", INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched", "PostRA Machine Instruction Scheduler", false, false) @@ -459,6 +456,7 @@ bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM, this->TM = &TM; AA = &Analyses.AA; LIS = &Analyses.LIS; + RegClassInfo = &Analyses.RegClassInfo; if (VerifyScheduling) { LLVM_DEBUG(LIS->dump()); @@ -468,7 +466,6 @@ bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM, else MF->verify(*MFAM, MSchedBanner, &errs()); } - RegClassInfo->runOnMachineFunction(*MF); // Instantiate the selected scheduler for this target, function, and // optimization level. @@ -564,8 +561,11 @@ bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) { auto &TM = getAnalysis().getTM(); auto &AA = getAnalysis().getAAResults(); auto &LIS = getAnalysis().getLIS(); + auto &RegClassInfo = + getAnalysis().getRCI(); + Impl.setLegacyPass(this); - return Impl.run(MF, TM, {MLI, MDT, AA, LIS}); + return Impl.run(MF, TM, {MLI, MDT, AA, LIS, RegClassInfo}); } MachineSchedulerPass::MachineSchedulerPass(const TargetMachine *TM) @@ -597,8 +597,9 @@ MachineSchedulerPass::run(MachineFunction &MF, .getManager(); auto &AA = FAM.getResult(MF.getFunction()); auto &LIS = MFAM.getResult(MF); + auto &RegClassInfo = MFAM.getResult(MF); Impl->setMFAM(&MFAM); - bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS}); + bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS, RegClassInfo}); if (!Changed) return PreservedAnalyses::all(); diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 173193bb6266c..393254d7ecaa7 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -41,6 +41,7 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachinePostDominators.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineSizeOpts.h" #include "llvm/CodeGen/RegisterClassInfo.h" @@ -134,7 +135,7 @@ class MachineSinking { MachineBlockFrequencyInfo *MBFI = nullptr; const MachineBranchProbabilityInfo *MBPI = nullptr; AliasAnalysis *AA = nullptr; - RegisterClassInfo RegClassInfo; + RegisterClassInfo *RegClassInfo = nullptr; TargetSchedModel SchedModel; // Required for split critical edge LiveIntervals *LIS; @@ -203,9 +204,10 @@ class MachineSinking { MachineLoopInfo *MLI, SlotIndexes *SI, LiveIntervals *LIS, MachineCycleInfo *CI, ProfileSummaryInfo *PSI, MachineBlockFrequencyInfo *MBFI, - const MachineBranchProbabilityInfo *MBPI, AliasAnalysis *AA) + const MachineBranchProbabilityInfo *MBPI, AliasAnalysis *AA, + RegisterClassInfo *RegClassInfo) : DT(DT), PDT(PDT), CI(CI), PSI(PSI), MBFI(MBFI), MBPI(MBPI), AA(AA), - LIS(LIS), SI(SI), LV(LV), MLI(MLI), + RegClassInfo(RegClassInfo), LIS(LIS), SI(SI), LV(LV), MLI(MLI), EnableSinkAndFold(EnableSinkAndFold) {} bool run(MachineFunction &MF); @@ -305,8 +307,10 @@ class MachineSinkingLegacy : public MachineFunctionPass { AU.addRequired(); AU.addRequired(); AU.addRequired(); + AU.addRequired(); AU.addPreserved(); AU.addPreserved(); + AU.addPreserved(); AU.addRequired(); if (UseBlockFreqInfo) AU.addRequired(); @@ -326,6 +330,7 @@ INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_END(MachineSinkingLegacy, DEBUG_TYPE, "Machine code sinking", false, false) @@ -772,8 +777,9 @@ MachineSinkingPass::run(MachineFunction &MF, auto *SI = MFAM.getCachedResult(MF); auto *LV = MFAM.getCachedResult(MF); auto *MLI = MFAM.getCachedResult(MF); + auto *RegClassInfo = &MFAM.getResult(MF); MachineSinking Impl(EnableSinkAndFold, DT, PDT, LV, MLI, SI, LIS, CI, PSI, - MBFI, MBPI, AA); + MBFI, MBPI, AA, RegClassInfo); bool Changed = Impl.run(MF); if (!Changed) return PreservedAnalyses::all(); @@ -818,9 +824,11 @@ bool MachineSinkingLegacy::runOnMachineFunction(MachineFunction &MF) { auto *LV = LVWrapper ? &LVWrapper->getLV() : nullptr; auto *MLIWrapper = getAnalysisIfAvailable(); auto *MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr; + auto *RegClassInfo = + &getAnalysis().getRCI(); MachineSinking Impl(EnableSinkAndFold, DT, PDT, LV, MLI, SI, LIS, CI, PSI, - MBFI, MBPI, AA); + MBFI, MBPI, AA, RegClassInfo); return Impl.run(MF); } @@ -832,8 +840,6 @@ bool MachineSinking::run(MachineFunction &MF) { TRI = STI->getRegisterInfo(); MRI = &MF.getRegInfo(); - RegClassInfo.runOnMachineFunction(MF); - bool EverMadeChange = false; while (true) { @@ -1201,7 +1207,7 @@ MachineSinking::getBBRegisterPressure(const MachineBasicBlock &MBB, RegPressureTracker RPTracker(Pressure); // Initialize the register pressure tracker. - RPTracker.init(MBB.getParent(), &RegClassInfo, nullptr, &MBB, MBB.end(), + RPTracker.init(MBB.getParent(), RegClassInfo, nullptr, &MBB, MBB.end(), /*TrackLaneMasks*/ false, /*TrackUntiedDefs=*/true); for (MachineBasicBlock::const_iterator MII = MBB.instr_end(), @@ -1237,7 +1243,7 @@ bool MachineSinking::registerPressureSetExceedsLimit( std::vector BBRegisterPressure = getBBRegisterPressure(MBB); for (; *PS != -1; PS++) if (Weight + BBRegisterPressure[*PS] >= - RegClassInfo.getRegPressureSetLimit(*PS)) + RegClassInfo->getRegPressureSetLimit(*PS)) return true; return false; } diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 039a473382732..8e9378905e33e 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -25,6 +25,7 @@ #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/ScheduleDAGInstrs.h" @@ -80,12 +81,13 @@ class PostRAScheduler { MachineLoopInfo *MLI = nullptr; AliasAnalysis *AA = nullptr; const TargetMachine *TM = nullptr; - RegisterClassInfo RegClassInfo; + RegisterClassInfo *RegClassInfo = nullptr; public: PostRAScheduler(MachineFunction &MF, MachineLoopInfo *MLI, AliasAnalysis *AA, - const TargetMachine *TM) - : TII(MF.getSubtarget().getInstrInfo()), MLI(MLI), AA(AA), TM(TM) {} + const TargetMachine *TM, RegisterClassInfo *RegClassInfo) + : TII(MF.getSubtarget().getInstrInfo()), MLI(MLI), AA(AA), TM(TM), + RegClassInfo(RegClassInfo) {} bool run(MachineFunction &MF); }; @@ -102,6 +104,8 @@ class PostRASchedulerLegacy : public MachineFunctionPass { AU.addPreserved(); AU.addRequired(); AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -202,8 +206,11 @@ class SchedulePostRATDList : public ScheduleDAGInstrs { char &llvm::PostRASchedulerID = PostRASchedulerLegacy::ID; -INITIALIZE_PASS(PostRASchedulerLegacy, DEBUG_TYPE, - "Post RA top-down list latency scheduler", false, false) +INITIALIZE_PASS_BEGIN(PostRASchedulerLegacy, DEBUG_TYPE, + "Post RA top-down list latency scheduler", false, false) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) +INITIALIZE_PASS_END(PostRASchedulerLegacy, DEBUG_TYPE, + "Post RA top-down list latency scheduler", false, false) SchedulePostRATDList::SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, @@ -292,11 +299,10 @@ bool PostRAScheduler::run(MachineFunction &MF) { } SmallVector CriticalPathRCs; Subtarget.getCriticalPathRCs(CriticalPathRCs); - RegClassInfo.runOnMachineFunction(MF); LLVM_DEBUG(dbgs() << "PostRAScheduler\n"); - SchedulePostRATDList Scheduler(MF, *MLI, AA, RegClassInfo, AntiDepMode, + SchedulePostRATDList Scheduler(MF, *MLI, AA, *RegClassInfo, AntiDepMode, CriticalPathRCs); // Loop over all of the basic blocks @@ -366,7 +372,9 @@ bool PostRASchedulerLegacy::runOnMachineFunction(MachineFunction &MF) { AliasAnalysis *AA = &getAnalysis().getAAResults(); const TargetMachine *TM = &getAnalysis().getTM(); - PostRAScheduler Impl(MF, MLI, AA, TM); + RegisterClassInfo *RegClassInfo = + &getAnalysis().getRCI(); + PostRAScheduler Impl(MF, MLI, AA, TM, RegClassInfo); return Impl.run(MF); } @@ -379,7 +387,9 @@ PostRASchedulerPass::run(MachineFunction &MF, auto &FAM = MFAM.getResult(MF) .getManager(); AliasAnalysis *AA = &FAM.getResult(MF.getFunction()); - PostRAScheduler Impl(MF, MLI, AA, TM); + RegisterClassInfo *RegClassInfo = + &FAM.getResult(MF.getFunction()); + PostRAScheduler Impl(MF, MLI, AA, TM, RegClassInfo); bool Changed = Impl.run(MF); if (!Changed) return PreservedAnalyses::all(); diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index dbd354f2ca2c4..228542af344a8 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -32,6 +32,7 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachinePassManager.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegisterClassInfo.h" @@ -132,7 +133,7 @@ class RegisterCoalescer : private LiveRangeEdit::Delegate { LiveIntervals *LIS = nullptr; SlotIndexes *SI = nullptr; const MachineLoopInfo *Loops = nullptr; - RegisterClassInfo RegClassInfo; + RegisterClassInfo *RegClassInfo = nullptr; /// Position and VReg of a PHI instruction during coalescing. struct PHIValPos { @@ -381,8 +382,9 @@ class RegisterCoalescer : private LiveRangeEdit::Delegate { RegisterCoalescer &operator=(RegisterCoalescer &&Other) = default; RegisterCoalescer(LiveIntervals *LIS, SlotIndexes *SI, - const MachineLoopInfo *Loops) - : LIS(LIS), SI(SI), Loops(Loops) {} + const MachineLoopInfo *Loops, + RegisterClassInfo *RegClassInfo) + : LIS(LIS), SI(SI), Loops(Loops), RegClassInfo(RegClassInfo) {} bool run(MachineFunction &MF); }; @@ -417,6 +419,7 @@ INITIALIZE_PASS_BEGIN(RegisterCoalescerLegacy, "register-coalescer", INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_END(RegisterCoalescerLegacy, "register-coalescer", "Register Coalescer", false, false) @@ -603,6 +606,8 @@ void RegisterCoalescerLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addPreserved(); AU.addPreservedID(MachineDominatorsID); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -2214,7 +2219,7 @@ bool RegisterCoalescer::joinCopy( // Removing sub-register copies can ease the register class constraints. // Make sure we attempt to inflate the register class of DstReg. - if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC())) + if (!CP.isPhys() && RegClassInfo->isProperSubClass(CP.getNewRC())) InflateRegs.push_back(CP.getDstReg()); // CopyMI has been erased by joinIntervals at this point. Remove it from @@ -4248,7 +4253,8 @@ RegisterCoalescerPass::run(MachineFunction &MF, auto &LIS = MFAM.getResult(MF); auto &Loops = MFAM.getResult(MF); auto *SI = MFAM.getCachedResult(MF); - RegisterCoalescer Impl(&LIS, SI, &Loops); + auto *RegClassInfo = &MFAM.getResult(MF); + RegisterCoalescer Impl(&LIS, SI, &Loops, RegClassInfo); if (!Impl.run(MF)) return PreservedAnalyses::all(); auto PA = getMachineFunctionPassPreservedAnalyses(); @@ -4264,8 +4270,10 @@ bool RegisterCoalescerLegacy::runOnMachineFunction(MachineFunction &MF) { auto *LIS = &getAnalysis().getLIS(); auto *Loops = &getAnalysis().getLI(); auto *SIWrapper = getAnalysisIfAvailable(); + auto *RegClassInfo = + &getAnalysis().getRCI(); SlotIndexes *SI = SIWrapper ? &SIWrapper->getSI() : nullptr; - RegisterCoalescer Impl(LIS, SI, Loops); + RegisterCoalescer Impl(LIS, SI, Loops, RegClassInfo); return Impl.run(MF); } @@ -4292,6 +4300,7 @@ bool RegisterCoalescer::run(MachineFunction &fn) { const TargetSubtargetInfo &STI = fn.getSubtarget(); TRI = STI.getRegisterInfo(); TII = STI.getInstrInfo(); + if (EnableGlobalCopies == cl::BOU_UNSET) JoinGlobalCopies = STI.enableJoinGlobalCopies(); else @@ -4321,8 +4330,6 @@ bool RegisterCoalescer::run(MachineFunction &fn) { DbgVRegToValues.clear(); buildVRegToDbgValueMap(fn); - RegClassInfo.runOnMachineFunction(fn); - // Join (coalesce) intervals if requested. if (EnableJoining) joinAllIntervals(); diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp index fa57eb30fac43..593c85d886202 100644 --- a/llvm/lib/CodeGen/ShrinkWrap.cpp +++ b/llvm/lib/CodeGen/ShrinkWrap.cpp @@ -65,6 +65,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" #include "llvm/CodeGen/MachinePostDominators.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/TargetFrameLowering.h" @@ -112,7 +113,7 @@ namespace { /// are safe for such insertion. class ShrinkWrap : public MachineFunctionPass { /// Hold callee-saved information. - RegisterClassInfo RCI; + RegisterClassInfo *RCI = nullptr; MachineDominatorTree *MDT = nullptr; MachinePostDominatorTree *MPDT = nullptr; @@ -223,7 +224,7 @@ class ShrinkWrap : public MachineFunctionPass { /// Initialize the pass for \p MF. void init(MachineFunction &MF) { - RCI.runOnMachineFunction(MF); + RCI = &getAnalysis().getRCI(); MDT = &getAnalysis().getDomTree(); MPDT = &getAnalysis().getPostDomTree(); Save = nullptr; @@ -265,6 +266,7 @@ class ShrinkWrap : public MachineFunctionPass { AU.addRequired(); AU.addRequired(); AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -292,6 +294,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_END(ShrinkWrap, DEBUG_TYPE, "Shrink Wrap Pass", false, false) bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS, @@ -350,7 +353,7 @@ bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS, // instruction we can ignore, otherwise we may pessimize shrinkwrapping. UseOrDefCSR = (!MI.isCall() && PhysReg == SP) || - RCI.getLastCalleeSavedAlias(PhysReg) || + RCI->getLastCalleeSavedAlias(PhysReg) || (!MI.isReturn() && TRI->isNonallocatableRegisterCalleeSave(PhysReg)); } else if (MO.isRegMask()) { // Check if this regmask clobbers any of the CSRs. diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 7dfff2479d3cf..94c14df2ef90d 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -126,6 +126,7 @@ #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" #include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/MachinePostDominators.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/MachineSink.h" diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp index c27ec8e6dc6b3..8322700d4a862 100644 --- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -35,9 +35,11 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/InitializePasses.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -108,7 +110,7 @@ class Chain; class AArch64A57FPLoadBalancing : public MachineFunctionPass { MachineRegisterInfo *MRI; const TargetRegisterInfo *TRI; - RegisterClassInfo RCI; + RegisterClassInfo *RCI = nullptr; public: static char ID; @@ -129,6 +131,8 @@ class AArch64A57FPLoadBalancing : public MachineFunctionPass { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -152,6 +156,7 @@ char AArch64A57FPLoadBalancing::ID = 0; INITIALIZE_PASS_BEGIN(AArch64A57FPLoadBalancing, DEBUG_TYPE, "AArch64 A57 FP Load-Balancing", false, false) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_END(AArch64A57FPLoadBalancing, DEBUG_TYPE, "AArch64 A57 FP Load-Balancing", false, false) @@ -317,7 +322,7 @@ bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) { MRI = &F.getRegInfo(); TRI = F.getRegInfo().getTargetRegisterInfo(); - RCI.runOnMachineFunction(F); + RCI = &getAnalysis().getRCI(); for (auto &MBB : F) { Changed |= runOnBasicBlock(MBB); @@ -515,7 +520,7 @@ int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C, // Make sure we allocate in-order, to get the cheapest registers first. unsigned RegClassID = ChainBegin->getDesc().operands()[0].RegClass; - auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); + auto Ord = RCI->getOrder(TRI->getRegClass(RegClassID)); for (auto Reg : Ord) { if (!Units.available(Reg)) continue; diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp index 205a45a045a42..c62ce8cb54d47 100644 --- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/LiveRegMatrix.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/VirtRegMap.h" @@ -42,7 +43,7 @@ class SIPreAllocateWWMRegs { LiveIntervals *LIS; LiveRegMatrix *Matrix; VirtRegMap *VRM; - RegisterClassInfo RegClassInfo; + const RegisterClassInfo &RegClassInfo; std::vector RegsToRewrite; #ifndef NDEBUG @@ -53,8 +54,8 @@ class SIPreAllocateWWMRegs { public: SIPreAllocateWWMRegs(LiveIntervals *LIS, LiveRegMatrix *Matrix, - VirtRegMap *VRM) - : LIS(LIS), Matrix(Matrix), VRM(VRM) {} + VirtRegMap *VRM, const RegisterClassInfo &RCI) + : LIS(LIS), Matrix(Matrix), VRM(VRM), RegClassInfo(RCI) {} bool run(MachineFunction &MF); }; @@ -70,6 +71,8 @@ class SIPreAllocateWWMRegsLegacy : public MachineFunctionPass { AU.addRequired(); AU.addRequired(); AU.addRequired(); + // TODO: Update RCI with the additional reserved registers the pass sets. + AU.addRequired(); AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -82,6 +85,7 @@ INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegsLegacy, DEBUG_TYPE, INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperLegacy) +INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass) INITIALIZE_PASS_END(SIPreAllocateWWMRegsLegacy, DEBUG_TYPE, "SI Pre-allocate WWM Registers", false, false) @@ -192,7 +196,8 @@ bool SIPreAllocateWWMRegsLegacy::runOnMachineFunction(MachineFunction &MF) { auto *LIS = &getAnalysis().getLIS(); auto *Matrix = &getAnalysis().getLRM(); auto *VRM = &getAnalysis().getVRM(); - return SIPreAllocateWWMRegs(LIS, Matrix, VRM).run(MF); + const auto &RCI = getAnalysis().getRCI(); + return SIPreAllocateWWMRegs(LIS, Matrix, VRM, RCI).run(MF); } bool SIPreAllocateWWMRegs::run(MachineFunction &MF) { @@ -204,8 +209,6 @@ bool SIPreAllocateWWMRegs::run(MachineFunction &MF) { TRI = &TII->getRegisterInfo(); MRI = &MF.getRegInfo(); - RegClassInfo.runOnMachineFunction(MF); - bool PreallocateSGPRSpillVGPRs = EnablePreallocateSGPRSpillVGPRs || MF.getFunction().hasFnAttribute("amdgpu-prealloc-sgpr-spill-vgprs"); @@ -265,6 +268,7 @@ SIPreAllocateWWMRegsPass::run(MachineFunction &MF, auto *LIS = &MFAM.getResult(MF); auto *Matrix = &MFAM.getResult(MF); auto *VRM = &MFAM.getResult(MF); - SIPreAllocateWWMRegs(LIS, Matrix, VRM).run(MF); + const auto &RCI = MFAM.getResult(MF); + SIPreAllocateWWMRegs(LIS, Matrix, VRM, RCI).run(MF); return PreservedAnalyses::all(); } diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll index e1481667a4ab7..3bb89fee3408a 100644 --- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll +++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll @@ -140,6 +140,7 @@ ; CHECK-NEXT: Machine Natural Loop Construction ; CHECK-NEXT: Machine Trace Metrics ; CHECK-NEXT: AArch64 Conditional Compares +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine InstCombiner ; CHECK-NEXT: AArch64 Conditional Branch Tuning @@ -157,6 +158,7 @@ ; CHECK-NEXT: Machine Common Subexpression Elimination ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Machine Cycle Info Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Machine code sinking ; CHECK-NEXT: Peephole Optimizations ; CHECK-NEXT: Remove dead machine instructions @@ -172,6 +174,7 @@ ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: Slot index numbering ; CHECK-NEXT: Live Interval Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Register Coalescer ; CHECK-NEXT: Rename Disconnected Subregister Components ; CHECK-NEXT: Machine Instruction Scheduler @@ -192,6 +195,7 @@ ; CHECK-NEXT: Machine Copy Propagation Pass ; CHECK-NEXT: Machine Loop Invariant Code Motion ; CHECK-NEXT: AArch64 Redundant Copy Elimination +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: A57 FP Anti-dependency breaker ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis ; CHECK-NEXT: Fixup Statepoint Caller Saved diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll index 4b6cc32522f5b..2cb9066187ff7 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll @@ -120,6 +120,7 @@ ; GCN-O0-NEXT: Live Interval Analysis ; GCN-O0-NEXT: Virtual Register Map ; GCN-O0-NEXT: Live Register Matrix +; GCN-O0-NEXT: Machine Register Class Info Analysis ; GCN-O0-NEXT: SI Pre-allocate WWM Registers ; GCN-O0-NEXT: Fast Register Allocator ; GCN-O0-NEXT: SI Lower WWM Copies @@ -327,6 +328,7 @@ ; GCN-O1-NEXT: Machine Common Subexpression Elimination ; GCN-O1-NEXT: MachinePostDominator Tree Construction ; GCN-O1-NEXT: Machine Cycle Info Analysis +; GCN-O1-NEXT: Machine Register Class Info Analysis ; GCN-O1-NEXT: Machine code sinking ; GCN-O1-NEXT: Peephole Optimizations ; GCN-O1-NEXT: Remove dead machine instructions @@ -350,6 +352,7 @@ ; GCN-O1-NEXT: Slot index numbering ; GCN-O1-NEXT: Live Interval Analysis ; GCN-O1-NEXT: Machine Natural Loop Construction +; GCN-O1-NEXT: Machine Register Class Info Analysis ; GCN-O1-NEXT: Register Coalescer ; GCN-O1-NEXT: Rename Disconnected Subregister Components ; GCN-O1-NEXT: Rewrite Partial Register Uses @@ -373,6 +376,7 @@ ; GCN-O1-NEXT: SI lower SGPR spill instructions ; GCN-O1-NEXT: Virtual Register Map ; GCN-O1-NEXT: Live Register Matrix +; GCN-O1-NEXT: Machine Register Class Info Analysis ; GCN-O1-NEXT: SI Pre-allocate WWM Registers ; GCN-O1-NEXT: Live Stack Slot Analysis ; GCN-O1-NEXT: Greedy Register Allocator @@ -398,6 +402,7 @@ ; GCN-O1-NEXT: MachinePostDominator Tree Construction ; GCN-O1-NEXT: Lazy Machine Block Frequency Analysis ; GCN-O1-NEXT: Machine Optimization Remark Emitter +; GCN-O1-NEXT: Machine Register Class Info Analysis ; GCN-O1-NEXT: Shrink Wrapping analysis ; GCN-O1-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; GCN-O1-NEXT: Machine Late Instructions Cleanup Pass @@ -632,6 +637,7 @@ ; GCN-O1-OPTS-NEXT: Machine Common Subexpression Elimination ; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction ; GCN-O1-OPTS-NEXT: Machine Cycle Info Analysis +; GCN-O1-OPTS-NEXT: Machine Register Class Info Analysis ; GCN-O1-OPTS-NEXT: Machine code sinking ; GCN-O1-OPTS-NEXT: Peephole Optimizations ; GCN-O1-OPTS-NEXT: Remove dead machine instructions @@ -662,6 +668,7 @@ ; GCN-O1-OPTS-NEXT: Slot index numbering ; GCN-O1-OPTS-NEXT: Live Interval Analysis ; GCN-O1-OPTS-NEXT: Machine Natural Loop Construction +; GCN-O1-OPTS-NEXT: Machine Register Class Info Analysis ; GCN-O1-OPTS-NEXT: Register Coalescer ; GCN-O1-OPTS-NEXT: Rename Disconnected Subregister Components ; GCN-O1-OPTS-NEXT: Rewrite Partial Register Uses @@ -686,6 +693,7 @@ ; GCN-O1-OPTS-NEXT: SI lower SGPR spill instructions ; GCN-O1-OPTS-NEXT: Virtual Register Map ; GCN-O1-OPTS-NEXT: Live Register Matrix +; GCN-O1-OPTS-NEXT: Machine Register Class Info Analysis ; GCN-O1-OPTS-NEXT: SI Pre-allocate WWM Registers ; GCN-O1-OPTS-NEXT: Live Stack Slot Analysis ; GCN-O1-OPTS-NEXT: Greedy Register Allocator @@ -711,6 +719,7 @@ ; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction ; GCN-O1-OPTS-NEXT: Lazy Machine Block Frequency Analysis ; GCN-O1-OPTS-NEXT: Machine Optimization Remark Emitter +; GCN-O1-OPTS-NEXT: Machine Register Class Info Analysis ; GCN-O1-OPTS-NEXT: Shrink Wrapping analysis ; GCN-O1-OPTS-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; GCN-O1-OPTS-NEXT: Machine Late Instructions Cleanup Pass @@ -950,6 +959,7 @@ ; GCN-O2-NEXT: Machine Common Subexpression Elimination ; GCN-O2-NEXT: MachinePostDominator Tree Construction ; GCN-O2-NEXT: Machine Cycle Info Analysis +; GCN-O2-NEXT: Machine Register Class Info Analysis ; GCN-O2-NEXT: Machine code sinking ; GCN-O2-NEXT: Peephole Optimizations ; GCN-O2-NEXT: Remove dead machine instructions @@ -980,6 +990,7 @@ ; GCN-O2-NEXT: Slot index numbering ; GCN-O2-NEXT: Live Interval Analysis ; GCN-O2-NEXT: Machine Natural Loop Construction +; GCN-O2-NEXT: Machine Register Class Info Analysis ; GCN-O2-NEXT: Register Coalescer ; GCN-O2-NEXT: Rename Disconnected Subregister Components ; GCN-O2-NEXT: Rewrite Partial Register Uses @@ -1005,6 +1016,7 @@ ; GCN-O2-NEXT: SI lower SGPR spill instructions ; GCN-O2-NEXT: Virtual Register Map ; GCN-O2-NEXT: Live Register Matrix +; GCN-O2-NEXT: Machine Register Class Info Analysis ; GCN-O2-NEXT: SI Pre-allocate WWM Registers ; GCN-O2-NEXT: Live Stack Slot Analysis ; GCN-O2-NEXT: Greedy Register Allocator @@ -1030,6 +1042,7 @@ ; GCN-O2-NEXT: MachinePostDominator Tree Construction ; GCN-O2-NEXT: Lazy Machine Block Frequency Analysis ; GCN-O2-NEXT: Machine Optimization Remark Emitter +; GCN-O2-NEXT: Machine Register Class Info Analysis ; GCN-O2-NEXT: Shrink Wrapping analysis ; GCN-O2-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; GCN-O2-NEXT: Machine Late Instructions Cleanup Pass @@ -1282,6 +1295,7 @@ ; GCN-O3-NEXT: Machine Common Subexpression Elimination ; GCN-O3-NEXT: MachinePostDominator Tree Construction ; GCN-O3-NEXT: Machine Cycle Info Analysis +; GCN-O3-NEXT: Machine Register Class Info Analysis ; GCN-O3-NEXT: Machine code sinking ; GCN-O3-NEXT: Peephole Optimizations ; GCN-O3-NEXT: Remove dead machine instructions @@ -1312,6 +1326,7 @@ ; GCN-O3-NEXT: Slot index numbering ; GCN-O3-NEXT: Live Interval Analysis ; GCN-O3-NEXT: Machine Natural Loop Construction +; GCN-O3-NEXT: Machine Register Class Info Analysis ; GCN-O3-NEXT: Register Coalescer ; GCN-O3-NEXT: Rename Disconnected Subregister Components ; GCN-O3-NEXT: Rewrite Partial Register Uses @@ -1337,6 +1352,7 @@ ; GCN-O3-NEXT: SI lower SGPR spill instructions ; GCN-O3-NEXT: Virtual Register Map ; GCN-O3-NEXT: Live Register Matrix +; GCN-O3-NEXT: Machine Register Class Info Analysis ; GCN-O3-NEXT: SI Pre-allocate WWM Registers ; GCN-O3-NEXT: Live Stack Slot Analysis ; GCN-O3-NEXT: Greedy Register Allocator @@ -1362,6 +1378,7 @@ ; GCN-O3-NEXT: MachinePostDominator Tree Construction ; GCN-O3-NEXT: Lazy Machine Block Frequency Analysis ; GCN-O3-NEXT: Machine Optimization Remark Emitter +; GCN-O3-NEXT: Machine Register Class Info Analysis ; GCN-O3-NEXT: Shrink Wrapping analysis ; GCN-O3-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; GCN-O3-NEXT: Machine Late Instructions Cleanup Pass diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll b/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll index 52ad7e5355207..16362d040b6ac 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll +++ b/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll @@ -21,6 +21,7 @@ ; DEFAULT-NEXT: SI lower SGPR spill instructions ; DEFAULT-NEXT: Virtual Register Map ; DEFAULT-NEXT: Live Register Matrix +; DEFAULT-NEXT: Machine Register Class Info Analysis ; DEFAULT-NEXT: SI Pre-allocate WWM Registers ; DEFAULT-NEXT: Live Stack Slot Analysis ; DEFAULT-NEXT: Greedy Register Allocator @@ -41,6 +42,7 @@ ; O0-NEXT: Live Interval Analysis ; O0-NEXT: Virtual Register Map ; O0-NEXT: Live Register Matrix +; O0-NEXT: Machine Register Class Info Analysis ; O0-NEXT: SI Pre-allocate WWM Registers ; O0-NEXT: Fast Register Allocator ; O0-NEXT: SI Lower WWM Copies @@ -63,6 +65,7 @@ ; BASIC-DEFAULT-NEXT: SI lower SGPR spill instructions ; BASIC-DEFAULT-NEXT: Virtual Register Map ; BASIC-DEFAULT-NEXT: Live Register Matrix +; BASIC-DEFAULT-NEXT: Machine Register Class Info Analysis ; BASIC-DEFAULT-NEXT: SI Pre-allocate WWM Registers ; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis ; BASIC-DEFAULT-NEXT: Bundle Machine CFG Edges @@ -89,6 +92,7 @@ ; DEFAULT-BASIC-NEXT: SI lower SGPR spill instructions ; DEFAULT-BASIC-NEXT: Virtual Register Map ; DEFAULT-BASIC-NEXT: Live Register Matrix +; DEFAULT-BASIC-NEXT: Machine Register Class Info Analysis ; DEFAULT-BASIC-NEXT: SI Pre-allocate WWM Registers ; DEFAULT-BASIC-NEXT: Live Stack Slot Analysis ; DEFAULT-BASIC-NEXT: Basic Register Allocator @@ -117,6 +121,7 @@ ; BASIC-BASIC-NEXT: SI lower SGPR spill instructions ; BASIC-BASIC-NEXT: Virtual Register Map ; BASIC-BASIC-NEXT: Live Register Matrix +; BASIC-BASIC-NEXT: Machine Register Class Info Analysis ; BASIC-BASIC-NEXT: SI Pre-allocate WWM Registers ; BASIC-BASIC-NEXT: Live Stack Slot Analysis ; BASIC-BASIC-NEXT: Basic Register Allocator diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll index 960d7305e66f6..877123f645804 100644 --- a/llvm/test/CodeGen/ARM/O3-pipeline.ll +++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll @@ -100,6 +100,7 @@ ; CHECK-NEXT: Machine Common Subexpression Elimination ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Machine Cycle Info Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Machine code sinking ; CHECK-NEXT: Peephole Optimizations ; CHECK-NEXT: Remove dead machine instructions @@ -127,6 +128,7 @@ ; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Slot index numbering ; CHECK-NEXT: Live Interval Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Register Coalescer ; CHECK-NEXT: Rename Disconnected Subregister Components ; CHECK-NEXT: Machine Instruction Scheduler @@ -153,6 +155,7 @@ ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Shrink Wrapping analysis ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Machine Late Instructions Cleanup Pass @@ -164,6 +167,7 @@ ; CHECK-NEXT: ARM load / store optimization pass ; CHECK-NEXT: ReachingDefAnalysis ; CHECK-NEXT: ARM Execution Domain Fix +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: BreakFalseDeps ; CHECK-NEXT: ARM pseudo instruction expansion pass ; CHECK-NEXT: Thumb2 instruction size reduce pass @@ -175,6 +179,7 @@ ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: Machine Natural Loop Construction ; CHECK-NEXT: PostRA Machine Instruction Scheduler +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Post RA top-down list latency scheduler ; CHECK-NEXT: MVE VPT block insertion pass ; CHECK-NEXT: ARM Indirect Thunks diff --git a/llvm/test/CodeGen/LoongArch/opt-pipeline.ll b/llvm/test/CodeGen/LoongArch/opt-pipeline.ll index 90d994909264a..47474be022233 100644 --- a/llvm/test/CodeGen/LoongArch/opt-pipeline.ll +++ b/llvm/test/CodeGen/LoongArch/opt-pipeline.ll @@ -105,6 +105,7 @@ ; LAXX-NEXT: Machine Common Subexpression Elimination ; LAXX-NEXT: MachinePostDominator Tree Construction ; LAXX-NEXT: Machine Cycle Info Analysis +; LAXX-NEXT: Machine Register Class Info Analysis ; LAXX-NEXT: Machine code sinking ; LAXX-NEXT: Peephole Optimizations ; LAXX-NEXT: Remove dead machine instructions @@ -121,6 +122,7 @@ ; LAXX-NEXT: MachineDominator Tree Construction ; LAXX-NEXT: Slot index numbering ; LAXX-NEXT: Live Interval Analysis +; LAXX-NEXT: Machine Register Class Info Analysis ; LAXX-NEXT: Register Coalescer ; LAXX-NEXT: Rename Disconnected Subregister Components ; LAXX-NEXT: Machine Instruction Scheduler @@ -148,6 +150,7 @@ ; LAXX-NEXT: MachinePostDominator Tree Construction ; LAXX-NEXT: Lazy Machine Block Frequency Analysis ; LAXX-NEXT: Machine Optimization Remark Emitter +; LAXX-NEXT: Machine Register Class Info Analysis ; LAXX-NEXT: Shrink Wrapping analysis ; LAXX-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; LAXX-NEXT: Machine Late Instructions Cleanup Pass @@ -158,6 +161,7 @@ ; LAXX-NEXT: Post-RA pseudo instruction expansion pass ; LAXX-NEXT: MachineDominator Tree Construction ; LAXX-NEXT: Machine Natural Loop Construction +; LAXX-NEXT: Machine Register Class Info Analysis ; LAXX-NEXT: Post RA top-down list latency scheduler ; LAXX-NEXT: Analyze Machine Code For Garbage Collection ; LAXX-NEXT: Machine Block Frequency Analysis diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll index 7cbb1a1c98873..dda900bc3d11e 100644 --- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll +++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll @@ -115,6 +115,7 @@ ; CHECK-NEXT: Machine Natural Loop Construction ; CHECK-NEXT: Machine Trace Metrics ; CHECK-NEXT: Early If-Conversion +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine InstCombiner ; CHECK-NEXT: Machine Block Frequency Analysis @@ -124,6 +125,7 @@ ; CHECK-NEXT: Machine Common Subexpression Elimination ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Machine Cycle Info Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Machine code sinking ; CHECK-NEXT: Peephole Optimizations ; CHECK-NEXT: Remove dead machine instructions @@ -149,6 +151,7 @@ ; CHECK-NEXT: Live Interval Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Modulo Software Pipelining ; CHECK-NEXT: Detect Dead Lanes ; CHECK-NEXT: Init Undef Pass @@ -161,6 +164,7 @@ ; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Slot index numbering ; CHECK-NEXT: Live Interval Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Register Coalescer ; CHECK-NEXT: Rename Disconnected Subregister Components ; CHECK-NEXT: Machine Instruction Scheduler @@ -189,6 +193,7 @@ ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Shrink Wrapping analysis ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Machine Late Instructions Cleanup Pass diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index beef7a574dc4f..3681fa14f681a 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -114,6 +114,7 @@ ; CHECK-NEXT: Machine Common Subexpression Elimination ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Machine Cycle Info Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Machine code sinking ; CHECK-NEXT: Peephole Optimizations ; CHECK-NEXT: Remove dead machine instructions @@ -138,6 +139,7 @@ ; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Slot index numbering ; CHECK-NEXT: Live Interval Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Register Coalescer ; CHECK-NEXT: Rename Disconnected Subregister Components ; CHECK-NEXT: Machine Instruction Scheduler @@ -172,6 +174,7 @@ ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Shrink Wrapping analysis ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Machine Late Instructions Cleanup Pass diff --git a/llvm/test/CodeGen/X86/opt-pipeline.ll b/llvm/test/CodeGen/X86/opt-pipeline.ll index d72f517cfb603..7c24bfec38bbe 100644 --- a/llvm/test/CodeGen/X86/opt-pipeline.ll +++ b/llvm/test/CodeGen/X86/opt-pipeline.ll @@ -105,6 +105,7 @@ ; CHECK-NEXT: Machine Natural Loop Construction ; CHECK-NEXT: Machine Trace Metrics ; CHECK-NEXT: Early If-Conversion +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine InstCombiner ; CHECK-NEXT: X86 cmov Conversion @@ -117,6 +118,7 @@ ; CHECK-NEXT: Machine Common Subexpression Elimination ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Machine Cycle Info Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Machine code sinking ; CHECK-NEXT: Peephole Optimizations ; CHECK-NEXT: Remove dead machine instructions @@ -142,6 +144,7 @@ ; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Slot index numbering ; CHECK-NEXT: Live Interval Analysis +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Register Coalescer ; CHECK-NEXT: Rename Disconnected Subregister Components ; CHECK-NEXT: Machine Instruction Scheduler @@ -175,6 +178,7 @@ ; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Shrink Wrapping analysis ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Machine Late Instructions Cleanup Pass @@ -187,6 +191,7 @@ ; CHECK-NEXT: Insert KCFI indirect call checks ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: Machine Natural Loop Construction +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: Post RA top-down list latency scheduler ; CHECK-NEXT: Analyze Machine Code For Garbage Collection ; CHECK-NEXT: Machine Block Frequency Analysis @@ -197,6 +202,7 @@ ; CHECK-NEXT: Implement the 'patchable-function' attribute ; CHECK-NEXT: ReachingDefAnalysis ; CHECK-NEXT: X86 Execution Dependency Fix +; CHECK-NEXT: Machine Register Class Info Analysis ; CHECK-NEXT: BreakFalseDeps ; CHECK-NEXT: X86 Indirect Branch Tracking ; CHECK-NEXT: X86 vzeroupper inserter From 05d58e1f22d6997dc19fb73627b7e030f64439b7 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 17 Mar 2025 20:10:28 +0800 Subject: [PATCH 2/3] Rename --- llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h | 6 +++--- llvm/include/llvm/Passes/MachinePassRegistry.def | 2 +- llvm/lib/CodeGen/MachineRegisterClassInfo.cpp | 8 ++++---- llvm/lib/CodeGen/MachineScheduler.cpp | 2 +- llvm/lib/CodeGen/MachineSink.cpp | 2 +- llvm/lib/CodeGen/PostRASchedulerList.cpp | 2 +- llvm/lib/CodeGen/RegisterCoalescer.cpp | 2 +- llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 2 +- 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h index dd8e34cab0bdd..dc66b2569217b 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h @@ -20,9 +20,9 @@ namespace llvm { -class MachineRegisterClassInfoAnalysis - : public AnalysisInfoMixin { - friend AnalysisInfoMixin; +class MachineRegisterClassAnalysis + : public AnalysisInfoMixin { + friend AnalysisInfoMixin; static AnalysisKey Key; diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index ebbaf36d02f70..331a052f5509a 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -114,7 +114,7 @@ MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter", MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree", MachinePostDominatorTreeAnalysis()) MACHINE_FUNCTION_ANALYSIS("machine-reg-class-info", - MachineRegisterClassInfoAnalysis()) + MachineRegisterClassAnalysis()) MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis()) MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) MACHINE_FUNCTION_ANALYSIS("regalloc-evict", RegAllocEvictionAdvisorAnalysis()) diff --git a/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp b/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp index 953de35068c16..b1e17ca783416 100644 --- a/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp @@ -19,9 +19,9 @@ using namespace llvm; INITIALIZE_PASS(MachineRegisterClassInfoWrapperPass, "machine-reg-class-info", "Machine Register Class Info Analysis", true, true) -MachineRegisterClassInfoAnalysis::Result -MachineRegisterClassInfoAnalysis::run(MachineFunction &MF, - MachineFunctionAnalysisManager &) { +MachineRegisterClassAnalysis::Result +MachineRegisterClassAnalysis::run(MachineFunction &MF, + MachineFunctionAnalysisManager &) { RegisterClassInfo RCI; RCI.runOnMachineFunction(MF); return RCI; @@ -43,4 +43,4 @@ bool MachineRegisterClassInfoWrapperPass::runOnMachineFunction( void MachineRegisterClassInfoWrapperPass::anchor() {} -AnalysisKey MachineRegisterClassInfoAnalysis::Key; +AnalysisKey MachineRegisterClassAnalysis::Key; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 4553648f7933e..c11d0966f26db 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -597,7 +597,7 @@ MachineSchedulerPass::run(MachineFunction &MF, .getManager(); auto &AA = FAM.getResult(MF.getFunction()); auto &LIS = MFAM.getResult(MF); - auto &RegClassInfo = MFAM.getResult(MF); + auto &RegClassInfo = MFAM.getResult(MF); Impl->setMFAM(&MFAM); bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS, RegClassInfo}); if (!Changed) diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 393254d7ecaa7..844664b5e3d6e 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -777,7 +777,7 @@ MachineSinkingPass::run(MachineFunction &MF, auto *SI = MFAM.getCachedResult(MF); auto *LV = MFAM.getCachedResult(MF); auto *MLI = MFAM.getCachedResult(MF); - auto *RegClassInfo = &MFAM.getResult(MF); + auto *RegClassInfo = &MFAM.getResult(MF); MachineSinking Impl(EnableSinkAndFold, DT, PDT, LV, MLI, SI, LIS, CI, PSI, MBFI, MBPI, AA, RegClassInfo); bool Changed = Impl.run(MF); diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 8e9378905e33e..873383f9ca41d 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -388,7 +388,7 @@ PostRASchedulerPass::run(MachineFunction &MF, .getManager(); AliasAnalysis *AA = &FAM.getResult(MF.getFunction()); RegisterClassInfo *RegClassInfo = - &FAM.getResult(MF.getFunction()); + &MFAM.getResult(MF); PostRAScheduler Impl(MF, MLI, AA, TM, RegClassInfo); bool Changed = Impl.run(MF); if (!Changed) diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 228542af344a8..70c7030877fe7 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -4253,7 +4253,7 @@ RegisterCoalescerPass::run(MachineFunction &MF, auto &LIS = MFAM.getResult(MF); auto &Loops = MFAM.getResult(MF); auto *SI = MFAM.getCachedResult(MF); - auto *RegClassInfo = &MFAM.getResult(MF); + auto *RegClassInfo = &MFAM.getResult(MF); RegisterCoalescer Impl(&LIS, SI, &Loops, RegClassInfo); if (!Impl.run(MF)) return PreservedAnalyses::all(); diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp index c62ce8cb54d47..9e0e87971d379 100644 --- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp @@ -268,7 +268,7 @@ SIPreAllocateWWMRegsPass::run(MachineFunction &MF, auto *LIS = &MFAM.getResult(MF); auto *Matrix = &MFAM.getResult(MF); auto *VRM = &MFAM.getResult(MF); - const auto &RCI = MFAM.getResult(MF); + const auto &RCI = MFAM.getResult(MF); SIPreAllocateWWMRegs(LIS, Matrix, VRM, RCI).run(MF); return PreservedAnalyses::all(); } From 7a207bc182f48abb8dab26d5f1953b9678ac5a7f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 18 Mar 2025 20:53:17 +0800 Subject: [PATCH 3/3] Add invalidate --- .../llvm/CodeGen/MachineRegisterClassInfo.h | 57 ------------------- llvm/include/llvm/CodeGen/RegisterClassInfo.h | 45 +++++++++++++++ llvm/lib/CodeGen/BreakFalseDeps.cpp | 1 - llvm/lib/CodeGen/CMakeLists.txt | 1 - llvm/lib/CodeGen/MachineCombiner.cpp | 1 - llvm/lib/CodeGen/MachinePipeliner.cpp | 1 - llvm/lib/CodeGen/MachineRegisterClassInfo.cpp | 46 --------------- llvm/lib/CodeGen/MachineScheduler.cpp | 1 - llvm/lib/CodeGen/MachineSink.cpp | 1 - llvm/lib/CodeGen/PostRASchedulerList.cpp | 1 - llvm/lib/CodeGen/RegisterClassInfo.cpp | 30 ++++++++++ llvm/lib/CodeGen/RegisterCoalescer.cpp | 1 - llvm/lib/CodeGen/ShrinkWrap.cpp | 1 - llvm/lib/Passes/PassBuilder.cpp | 2 +- .../AArch64/AArch64A57FPLoadBalancing.cpp | 1 - .../Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 1 - 16 files changed, 76 insertions(+), 115 deletions(-) delete mode 100644 llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h delete mode 100644 llvm/lib/CodeGen/MachineRegisterClassInfo.cpp diff --git a/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h deleted file mode 100644 index dc66b2569217b..0000000000000 --- a/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h +++ /dev/null @@ -1,57 +0,0 @@ -//=- MachineRegisterClassInfo.h - Machine Register Class Info -----*- C++ -*-=// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This analysis calculates register class info via RegisterClassInfo. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H -#define LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H - -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachinePassManager.h" -#include "llvm/CodeGen/RegisterClassInfo.h" -#include "llvm/Pass.h" - -namespace llvm { - -class MachineRegisterClassAnalysis - : public AnalysisInfoMixin { - friend AnalysisInfoMixin; - - static AnalysisKey Key; - -public: - using Result = RegisterClassInfo; - - Result run(MachineFunction &, MachineFunctionAnalysisManager &); -}; - -class MachineRegisterClassInfoWrapperPass : public MachineFunctionPass { - virtual void anchor(); - - RegisterClassInfo RCI; - -public: - static char ID; - - MachineRegisterClassInfoWrapperPass(); - - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesAll(); - MachineFunctionPass::getAnalysisUsage(AU); - } - - bool runOnMachineFunction(MachineFunction &MF) override; - - RegisterClassInfo &getRCI() { return RCI; } - const RegisterClassInfo &getRCI() const { return RCI; } -}; -} // namespace llvm - -#endif diff --git a/llvm/include/llvm/CodeGen/RegisterClassInfo.h b/llvm/include/llvm/CodeGen/RegisterClassInfo.h index 800bebea0dddb..e6bb952a6d3e7 100644 --- a/llvm/include/llvm/CodeGen/RegisterClassInfo.h +++ b/llvm/include/llvm/CodeGen/RegisterClassInfo.h @@ -19,6 +19,8 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/MC/MCRegister.h" #include @@ -26,6 +28,8 @@ namespace llvm { +class MachineRegisterClassAnalysis; + class RegisterClassInfo { struct RCInfo { unsigned Tag = 0; @@ -89,6 +93,14 @@ class RegisterClassInfo { /// before any other methods are used. void runOnMachineFunction(const MachineFunction &MF); + bool invalidate(MachineFunction &, const PreservedAnalyses &PA, + MachineFunctionAnalysisManager::Invalidator &) { + // Check whether the analysis has been explicitly invalidated. Otherwise, + // it's stateless and remains preserved. + auto PAC = PA.getChecker(); + return !PAC.preservedWhenStateless(); + } + /// getNumAllocatableRegs - Returns the number of actually allocatable /// registers in RC in the current function. unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { @@ -153,6 +165,39 @@ class RegisterClassInfo { unsigned computePSetLimit(unsigned Idx) const; }; +class MachineRegisterClassAnalysis + : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + + static AnalysisKey Key; + +public: + using Result = RegisterClassInfo; + + Result run(MachineFunction &, MachineFunctionAnalysisManager &); +}; + +class MachineRegisterClassInfoWrapperPass : public MachineFunctionPass { + virtual void anchor(); + + RegisterClassInfo RCI; + +public: + static char ID; + + MachineRegisterClassInfoWrapperPass(); + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + RegisterClassInfo &getRCI() { return RCI; } + const RegisterClassInfo &getRCI() const { return RCI; } +}; + } // end namespace llvm #endif // LLVM_CODEGEN_REGISTERCLASSINFO_H diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp index 6d80e82beafa4..e1e2ff673fbd7 100644 --- a/llvm/lib/CodeGen/BreakFalseDeps.cpp +++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp @@ -20,7 +20,6 @@ #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/ReachingDefAnalysis.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/TargetInstrInfo.h" diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt index 4b2640325a360..0e237ba31a8ca 100644 --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -142,7 +142,6 @@ add_llvm_component_library(LLVMCodeGen MachinePipeliner.cpp MachinePostDominators.cpp MachineRegionInfo.cpp - MachineRegisterClassInfo.cpp MachineRegisterInfo.cpp MachineScheduler.cpp MachineSink.cpp diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp index 483890412e4f4..37ef58aafefae 100644 --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -19,7 +19,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineSizeOpts.h" #include "llvm/CodeGen/MachineTraceMetrics.h" diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 534f932ce6624..a2202e9a1a059 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -58,7 +58,6 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineOperand.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ModuloSchedule.h" #include "llvm/CodeGen/Register.h" diff --git a/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp b/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp deleted file mode 100644 index b1e17ca783416..0000000000000 --- a/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp +++ /dev/null @@ -1,46 +0,0 @@ -//===- MachineRegisterClassInfo.cpp - Machine Register Class Info ---------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This analysis calculates register class info via RegisterClassInfo. -// -//===----------------------------------------------------------------------===// - -#include "llvm/CodeGen/MachineRegisterClassInfo.h" -#include "llvm/CodeGen/RegisterClassInfo.h" -#include "llvm/InitializePasses.h" - -using namespace llvm; - -INITIALIZE_PASS(MachineRegisterClassInfoWrapperPass, "machine-reg-class-info", - "Machine Register Class Info Analysis", true, true) - -MachineRegisterClassAnalysis::Result -MachineRegisterClassAnalysis::run(MachineFunction &MF, - MachineFunctionAnalysisManager &) { - RegisterClassInfo RCI; - RCI.runOnMachineFunction(MF); - return RCI; -} - -char MachineRegisterClassInfoWrapperPass::ID = 0; - -MachineRegisterClassInfoWrapperPass::MachineRegisterClassInfoWrapperPass() - : MachineFunctionPass(ID), RCI() { - PassRegistry &Registry = *PassRegistry::getPassRegistry(); - initializeMachineRegisterClassInfoWrapperPassPass(Registry); -} - -bool MachineRegisterClassInfoWrapperPass::runOnMachineFunction( - MachineFunction &MF) { - RCI.runOnMachineFunction(MF); - return false; -} - -void MachineRegisterClassInfoWrapperPass::anchor() {} - -AnalysisKey MachineRegisterClassAnalysis::Key; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index c11d0966f26db..5a292257707bd 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -31,7 +31,6 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachinePassRegistry.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterPressure.h" diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 844664b5e3d6e..f6bc9520a429c 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -41,7 +41,6 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachinePostDominators.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineSizeOpts.h" #include "llvm/CodeGen/RegisterClassInfo.h" diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 873383f9ca41d..9f0d2e4623250 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -25,7 +25,6 @@ #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/ScheduleDAGInstrs.h" diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp index 40fc35a16335f..b92d5b1424724 100644 --- a/llvm/lib/CodeGen/RegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" +#include "llvm/InitializePasses.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -233,3 +234,32 @@ unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const { unsigned NReserved = RC->getNumRegs() - NAllocatableRegs; return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved; } + +INITIALIZE_PASS(MachineRegisterClassInfoWrapperPass, "machine-reg-class-info", + "Machine Register Class Info Analysis", true, true) + +MachineRegisterClassAnalysis::Result +MachineRegisterClassAnalysis::run(MachineFunction &MF, + MachineFunctionAnalysisManager &) { + RegisterClassInfo RCI; + RCI.runOnMachineFunction(MF); + return RCI; +} + +char MachineRegisterClassInfoWrapperPass::ID = 0; + +MachineRegisterClassInfoWrapperPass::MachineRegisterClassInfoWrapperPass() + : MachineFunctionPass(ID), RCI() { + PassRegistry &Registry = *PassRegistry::getPassRegistry(); + initializeMachineRegisterClassInfoWrapperPassPass(Registry); +} + +bool MachineRegisterClassInfoWrapperPass::runOnMachineFunction( + MachineFunction &MF) { + RCI.runOnMachineFunction(MF); + return false; +} + +void MachineRegisterClassInfoWrapperPass::anchor() {} + +AnalysisKey MachineRegisterClassAnalysis::Key; diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 70c7030877fe7..e9e02860ba6e1 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -32,7 +32,6 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachinePassManager.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegisterClassInfo.h" diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp index 593c85d886202..be5bbe282077a 100644 --- a/llvm/lib/CodeGen/ShrinkWrap.cpp +++ b/llvm/lib/CodeGen/ShrinkWrap.cpp @@ -65,7 +65,6 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" #include "llvm/CodeGen/MachinePostDominators.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/TargetFrameLowering.h" diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 94c14df2ef90d..1a1c74d193669 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -126,7 +126,6 @@ #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" #include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/MachinePostDominators.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/MachineSink.h" @@ -144,6 +143,7 @@ #include "llvm/CodeGen/RegAllocPriorityAdvisor.h" #include "llvm/CodeGen/RegUsageInfoCollector.h" #include "llvm/CodeGen/RegUsageInfoPropagate.h" +#include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterCoalescerPass.h" #include "llvm/CodeGen/RegisterUsageInfo.h" #include "llvm/CodeGen/RemoveRedundantDebugValues.h" diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp index 8322700d4a862..65a631759b89a 100644 --- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -35,7 +35,6 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp index 9e0e87971d379..c4a0d81c8f1bd 100644 --- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp @@ -21,7 +21,6 @@ #include "llvm/CodeGen/LiveRegMatrix.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineRegisterClassInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/VirtRegMap.h"