From 0b627173e09cde186c98ad67e678bb5120315898 Mon Sep 17 00:00:00 2001 From: klensy Date: Fri, 20 Dec 2024 15:22:53 +0300 Subject: [PATCH 1/2] fix typo --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index a27c030237c87..1dce6189f0c29 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -18396,7 +18396,7 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) { EVT VT = A.getValueType(); SDValue Op0 = A.getOperand(0); SDValue Op1 = A.getOperand(1); - if (Op0.getOpcode() != Op0.getOpcode() || + if (Op0.getOpcode() != Op1.getOpcode() || (Op0.getOpcode() != ISD::ZERO_EXTEND && Op0.getOpcode() != ISD::SIGN_EXTEND)) return SDValue(); From 6b8dc458a9424953a448838b9a3001bc99ad999b Mon Sep 17 00:00:00 2001 From: klensy Date: Fri, 20 Dec 2024 16:03:23 +0300 Subject: [PATCH 2/2] add test --- llvm/test/CodeGen/AArch64/vecreduce-add.ll | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll index 8473f45f6c803..5d6b523f1549a 100644 --- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll +++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll @@ -72,6 +72,24 @@ entry: ret i64 %z } +define i64 @add_v4i32_v4i64_zsext(<4 x i32> %xi) { +; CHECK-LABEL: add_v4i32_v4i64_zsext: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ushll v1.2d, v0.2s, #0 +; CHECK-NEXT: saddw2 v0.2d, v1.2d, v0.4s +; CHECK-NEXT: addp d0, v0.2d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret +entry: + %x = shufflevector <4 x i32> %xi, <4 x i32> %xi, <2 x i32> + %y = shufflevector <4 x i32> %xi, <4 x i32> %xi, <2 x i32> + %xx = zext <2 x i32> %x to <2 x i64> + %yy = sext <2 x i32> %y to <2 x i64> + %zz = add <2 x i64> %xx, %yy + %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %zz) + ret i64 %z +} + define i64 @add_v2i32_v2i64_zext(<2 x i32> %x) { ; CHECK-LABEL: add_v2i32_v2i64_zext: ; CHECK: // %bb.0: // %entry