diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h index 07722090c30ee..b425aa59251fa 100644 --- a/clang/lib/Headers/avx10_2convertintrin.h +++ b/clang/lib/Headers/avx10_2convertintrin.h @@ -24,24 +24,157 @@ __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ __min_vector_width__(256))) +// clang-format off + +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 128-bit vector +/// containing FP16 elements. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF i < 4 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4]) +/// FI +/// +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __A +/// A 128-bit vector of [4 x float]. +/// \param __B +/// A 128-bit vector of [4 x float]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A, __m128 __B) { return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask( (__v4sf)__A, (__v4sf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)(-1)); } +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 128-bit vector +/// containing FP16 elements. Merging mask \a __U is used to determine if given +/// element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// IF i < 4 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4]) +/// FI +/// ELSE +/// dst.fp16[i] := __W.fp16[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __W +/// A 128-bit vector of [8 x fp16]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [4 x float]. +/// \param __B +/// A 128-bit vector of [4 x float]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) { return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask( (__v4sf)__A, (__v4sf)__B, (__v8hf)__W, (__mmask8)__U); } +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 128-bit vector +/// containing FP16 elements. Zeroing mask \a __U is used to determine if given +/// element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// IF i < 4 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4]) +/// FI +/// ELSE +/// dst.fp16[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [4 x float]. +/// \param __B +/// A 128-bit vector of [4 x float]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// then zero is taken instead. static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) { return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask( (__v4sf)__A, (__v4sf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)__U); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 256-bit vector +/// containing FP16 elements. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF i < 8 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8]) +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __A +/// A 256-bit vector of [8 x float]. +/// \param __B +/// A 256-bit vector of [8 x float]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A, __m256 __B) { return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask( @@ -49,6 +182,44 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A, _MM_FROUND_CUR_DIRECTION); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 256-bit vector +/// containing FP16 elements. Merging mask \a __U is used to determine if given +/// element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8]) +/// FI +/// ELSE +/// dst.fp16[i] := __W.fp16[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __W +/// A 256-bit vector of [16 x fp16]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [8 x float]. +/// \param __B +/// A 256-bit vector of [8 x float]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) { return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask( @@ -56,6 +227,42 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) { _MM_FROUND_CUR_DIRECTION); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 256-bit vector +/// containing FP16 elements. Zeroing mask \a __U is used to determine if given +/// element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8]) +/// FI +/// ELSE +/// dst.fp16[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [8 x float]. +/// \param __B +/// A 256-bit vector of [8 x float]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// then zero is taken instead. static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) { return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask( @@ -63,32 +270,240 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) { _MM_FROUND_CUR_DIRECTION); } -#define _mm256_cvtx_round2ps_ph(A, B, R) \ +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 256-bit vector +/// containing FP16 elements. Rounding mode \a __R needs to be provided. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF i < 8 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8]) +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __A +/// A 256-bit vector of [8 x float]. +/// \param __B +/// A 256-bit vector of [8 x float]. +/// \param __R +/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or +/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following: +/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF, +/// _MM_FROUND_TO_ZERO. +/// \returns +/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. +#define _mm256_cvtx_round2ps_ph(__A, __B, __R) \ ((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \ - (__v8sf)(A), (__v8sf)(B), (__v16hf)_mm256_undefined_ph(), \ - (__mmask16)(-1), (const int)(R))) - -#define _mm256_mask_cvtx_round2ps_ph(W, U, A, B, R) \ + (__v8sf)(__A), (__v8sf)(__B), (__v16hf)_mm256_undefined_ph(), \ + (__mmask16)(-1), (const int)(__R))) + +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 256-bit vector +/// containing FP16 elements. Merging mask \a __U is used to determine if given +/// element should be taken from \a __W instead. Rounding mode \a __R needs to +/// be provided. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8]) +/// FI +/// ELSE +/// dst.fp16[i] := __W.fp16[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __W +/// A 256-bit vector of [16 x fp16]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [8 x float]. +/// \param __B +/// A 256-bit vector of [8 x float]. +/// \param __R +/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or +/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following: +/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF, +/// _MM_FROUND_TO_ZERO. +/// \returns +/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. +#define _mm256_mask_cvtx_round2ps_ph(__W, __U, __A, __B, __R) \ ((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \ - (__v8sf)(A), (__v8sf)(B), (__v16hf)(W), (__mmask16)(U), (const int)(R))) - -#define _mm256_maskz_cvtx_round2ps_ph(U, A, B, R) \ + (__v8sf)(__A), (__v8sf)(__B), (__v16hf)(__W), (__mmask16)(__U), (const int)(__R))) + +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed +/// single-precision (32-bit) floating-point elements to a 256-bit vector +/// containing FP16 elements. Zeroing mask \a __U is used to determine if given +/// element should be zeroed instead. Rounding mode \a __R needs to be provided. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i]) +/// ELSE +/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8]) +/// FI +/// ELSE +/// dst.fp16[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [8 x float]. +/// \param __B +/// A 256-bit vector of [8 x float]. +/// \param __R +/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or +/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following: +/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF, +/// _MM_FROUND_TO_ZERO. +/// \returns +/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// then zero is taken instead. +#define _mm256_maskz_cvtx_round2ps_ph(__U, __A, __B, __R) \ ((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \ - (__v8sf)(A), (__v8sf)(B), (__v16hf)(_mm256_setzero_ph()), \ - (__mmask16)(U), (const int)(R))) - -static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtbiasph_bf8(__m128i __A, - __m128h __B) { + (__v8sf)(__A), (__v8sf)(__B), (__v16hf)(_mm256_setzero_ph()), \ + (__mmask16)(__U), (const int)(__R))) + +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// converted elements from \a __B using biases from \a __A; higher order +/// elements are zeroed. +static __inline__ __m128i __DEFAULT_FN_ATTRS128 +_mm_cvtbiasph_bf8(__m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask( (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1); } +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if +/// given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// converted elements from \a __B, using biases from \a __A; higher order +/// elements are zeroed. If corresponding mask bit is not set, then element +/// from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask( (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U); } +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if +/// given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// converted elements from \a __B, using biases from \a __A; higher order +/// elements are zeroed. If corresponding mask bit is not set, then element +/// is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask( @@ -96,6 +511,29 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) { (__mmask8)__U); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Elements correspond to the +/// converted elements from \a __B using biases from \a __A. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask( @@ -103,12 +541,76 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) { (__mmask16)-1); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if +/// given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Elements correspond to the converted +/// elements from \a __B, using biases from \a __A. If corresponding mask bit +/// is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8( __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask( (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if +/// given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Elements correspond to the converted +/// elements from \a __B, using biases from \a __A. If corresponding mask bit +/// is not set, then element is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask( @@ -116,18 +618,107 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) { (__mmask16)__U); } +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// converted elements from \a __B using biases from \a __A; higher order +/// elements are zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask( (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1); } -static __inline__ __m128i __DEFAULT_FN_ATTRS128 -_mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) { - return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask( - (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U); -} - +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U +/// is used to determine if given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// converted elements from \a __B, using biases from \a __A; higher order +/// elements are zeroed. If corresponding mask bit is not set, then element +/// from \a __W is taken instead. +static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtbiassph_bf8(__m128i + __W, __mmask8 __U, __m128i __A, __m128h __B) { return + (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask( (__v16qi)__A, + (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U); } + +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U +/// is used to determine if given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// converted elements from \a __B, using biases from \a __A; higher order +/// elements are zeroed. If corresponding mask bit is not set, then element +/// is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask( @@ -135,6 +726,30 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) { (__mmask8)__U); } + +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Elements correspond to the +/// converted elements from \a __B using biases from \a __A. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask( @@ -142,12 +757,76 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) { (__mmask16)-1); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U +/// is used to determine if given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Elements correspond to the converted +/// elements from \a __B, using biases from \a __A. If corresponding mask bit +/// is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8( __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask( (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U +/// is used to determine if given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Elements correspond to the converted +/// elements from \a __B, using biases from \a __A. If corresponding mask bit +/// is not set, then element is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask( @@ -155,18 +834,108 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) { (__mmask16)__U); } -static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtbiasph_hf8(__m128i __A, - __m128h __B) { +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// converted elements from \a __B using biases from \a __A; higher order +/// elements are zeroed. +static __inline__ __m128i __DEFAULT_FN_ATTRS128 +_mm_cvtbiasph_hf8(__m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask( (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1); } +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if +/// given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// converted elements from \a __B, using biases from \a __A; higher order +/// elements are zeroed. If corresponding mask bit is not set, then element +/// from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask( (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U); } +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if +/// given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// converted elements from \a __B, using biases from \a __A; higher order +/// elements are zeroed. If corresponding mask bit is not set, then element +/// is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask( @@ -174,6 +943,29 @@ _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) { (__mmask8)__U); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x half]. +/// \param __B +/// A 256-bit vector of [16 x i16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Elements correspond to the +/// converted elements from \a __B using biases from \a __A. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask( @@ -181,12 +973,76 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) { (__mmask16)-1); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if +/// given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Elements correspond to the converted +/// elements from \a __B, using biases from \a __A. If corresponding mask bit +/// is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8( __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask( (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if +/// given element should be taken zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x half]. +/// \param __B +/// A 256-bit vector of [16 x i16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Elements correspond to the converted +/// elements from \a __B, using biases from \a __A. If corresponding mask bit +/// is not set, then element is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask( @@ -194,18 +1050,108 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) { (__mmask16)__U); } +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S`instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// converted elements from \a __B using biases from \a __A; higher order +/// elements are zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask( (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1); } +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U +/// is used to determine if given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// converted elements from \a __B, using biases from \a __A; higher order +/// elements are zeroed. If corresponding mask bit is not set, then element +/// from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask( (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U); } +/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U +/// is used to determine if given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x int16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// converted elements from \a __B, using biases from \a __A; higher order +/// elements are zeroed. If corresponding mask bit is not set, then element +/// is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask( @@ -213,6 +1159,29 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) { (__mmask8)__U); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Elements correspond to the +/// converted elements from \a __B using biases from \a __A. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask( @@ -220,12 +1189,76 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) { (__mmask16)-1); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U +/// is used to determine if given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Elements correspond to the converted +/// elements from \a __B, using biases from \a __A. If corresponding mask bit +/// is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8( __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask( (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements +/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each +/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U +/// is used to determine if given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i]) +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x int16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Elements correspond to the converted +/// elements from \a __B, using biases from \a __A. If corresponding mask bit +/// is not set, then element is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) { return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask( @@ -233,17 +1266,119 @@ _mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) { (__mmask16)__U); } +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF i < 8 +/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8]) +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A, - __m128h __B) { - return (__m128i)__builtin_ia32_vcvt2ph2bf8_128((__v8hf)(__A), (__v8hf)(__B)); -} - + __m128h __B) { + return (__m128i)__builtin_ia32_vcvt2ph2bf8_128((__v8hf)(__A), + (__v8hf)(__B)); +} + +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8]) +/// FI +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( (__mmask16)__U, (__v16qi)_mm_cvt2ph_bf8(__A, __B), (__v16qi)__W); } +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8]) +/// FI +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// zero is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( @@ -251,18 +1386,119 @@ _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) { (__v16qi)(__m128i)_mm_setzero_si128()); } -static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_cvt2ph_bf8(__m256h __A, - __m256h __B) { - return (__m256i)__builtin_ia32_vcvt2ph2bf8_256((__v16hf)(__A), - (__v16hf)(__B)); -} - +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF i < 16 +/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16]) +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_mask_cvt2ph_bf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { +_mm256_cvt2ph_bf8(__m256h __A, __m256h __B) { + return (__m256i)__builtin_ia32_vcvt2ph2bf8_256((__v16hf)(__A), + (__v16hf)(__B)); +} + +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF __U[i] +/// IF i < 16 +/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16]) +/// FI +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction. +/// +/// \param __W +/// A 256-bit vector of [32 x bf8]. +/// \param __U +/// A 32-bit merging mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. +static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8( + __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( (__mmask32)__U, (__v32qi)_mm256_cvt2ph_bf8(__A, __B), (__v32qi)__W); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF __U[i] +/// IF i < 16 +/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16]) +/// FI +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction. +/// +/// \param __U +/// A 32-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// zero is taken instead. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( @@ -270,17 +1506,120 @@ _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) { (__v32qi)(__m256i)_mm256_setzero_si256()); } -static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts2ph_bf8(__m128h __A, - __m128h __B) { - return (__m128i)__builtin_ia32_vcvt2ph2bf8s_128((__v8hf)(__A), (__v8hf)(__B)); -} - +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements. +/// Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF i < 8 +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8]) +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. +static __inline__ __m128i __DEFAULT_FN_ATTRS128 +_mm_cvts2ph_bf8(__m128h __A, __m128h __B) { + return (__m128i)__builtin_ia32_vcvt2ph2bf8s_128((__v8hf)(__A), + (__v8hf)(__B)); +} + +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8]) +/// FI +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( (__mmask16)__U, (__v16qi)_mm_cvts2ph_bf8(__A, __B), (__v16qi)__W); } +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8]) +/// FI +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// zero is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( @@ -288,18 +1627,120 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) { (__v16qi)(__m128i)_mm_setzero_si128()); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements. +/// Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF i < 16 +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16]) +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_vcvt2ph2bf8s_256((__v16hf)(__A), - (__v16hf)(__B)); -} - -static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_mask_cvts2ph_bf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { + (__v16hf)(__B)); +} + +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF __U[i] +/// IF i < 16 +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16]) +/// FI +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction. +/// +/// \param __W +/// A 256-bit vector of [32 x bf8]. +/// \param __U +/// A 32-bit merging mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. +static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8( + __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( (__mmask32)__U, (__v32qi)_mm256_cvts2ph_bf8(__A, __B), (__v32qi)__W); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF __U[i] +/// IF i < 16 +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16]) +/// FI +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction. +/// +/// \param __U +/// A 32-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// zero is taken instead. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( @@ -307,17 +1748,119 @@ _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) { (__v32qi)(__m256i)_mm256_setzero_si256()); } +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF i < 8 +/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8]) +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A, - __m128h __B) { - return (__m128i)__builtin_ia32_vcvt2ph2hf8_128((__v8hf)(__A), (__v8hf)(__B)); -} - + __m128h __B) { + return (__m128i)__builtin_ia32_vcvt2ph2hf8_128((__v8hf)(__A), + (__v8hf)(__B)); +} + +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8]) +/// FI +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( (__mmask16)__U, (__v16qi)_mm_cvt2ph_hf8(__A, __B), (__v16qi)__W); } +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8]) +/// FI +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// zero is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( @@ -325,18 +1868,119 @@ _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) { (__v16qi)(__m128i)_mm_setzero_si128()); } -static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_cvt2ph_hf8(__m256h __A, - __m256h __B) { - return (__m256i)__builtin_ia32_vcvt2ph2hf8_256((__v16hf)(__A), - (__v16hf)(__B)); -} - +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF i < 16 +/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16]) +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_mask_cvt2ph_hf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { +_mm256_cvt2ph_hf8(__m256h __A, __m256h __B) { + return (__m256i)__builtin_ia32_vcvt2ph2hf8_256((__v16hf)(__A), + (__v16hf)(__B)); +} + +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF __U[i] +/// IF i < 16 +/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16]) +/// FI +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction. +/// +/// \param __W +/// A 256-bit vector of [32 x hf8]. +/// \param __U +/// A 32-bit merging mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. +static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8( + __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( (__mmask32)__U, (__v32qi)_mm256_cvt2ph_hf8(__A, __B), (__v32qi)__W); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF __U[i] +/// IF i < 16 +/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16]) +/// FI +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction. +/// +/// \param __U +/// A 32-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// zero is taken instead. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( @@ -344,17 +1988,120 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) { (__v32qi)(__m256i)_mm256_setzero_si256()); } -static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts2ph_hf8(__m128h __A, - __m128h __B) { - return (__m128i)__builtin_ia32_vcvt2ph2hf8s_128((__v8hf)(__A), (__v8hf)(__B)); -} - +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements. +/// Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF i < 8 +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8]) +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. +static __inline__ __m128i __DEFAULT_FN_ATTRS128 +_mm_cvts2ph_hf8(__m128h __A, __m128h __B) { + return (__m128i)__builtin_ia32_vcvt2ph2hf8s_128((__v8hf)(__A), + (__v8hf)(__B)); +} + +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8]) +/// FI +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( (__mmask16)__U, (__v16qi)_mm_cvts2ph_hf8(__A, __B), (__v16qi)__W); } +/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// IF i < 8 +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8]) +/// FI +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \param __B +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// zero is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( @@ -362,18 +2109,120 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) { (__v16qi)(__m128i)_mm_setzero_si128()); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements. +/// Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF i < 16 +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16]) +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_vcvt2ph2hf8s_256((__v16hf)(__A), - (__v16hf)(__B)); -} - -static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_mask_cvts2ph_hf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { + (__v16hf)(__B)); +} + +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF __U[i] +/// IF i < 16 +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16]) +/// FI +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction. +/// +/// \param __W +/// A 256-bit vector of [32 x hf8]. +/// \param __U +/// A 32-bit merging mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. +static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8( + __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( (__mmask32)__U, (__v32qi)_mm256_cvts2ph_hf8(__A, __B), (__v32qi)__W); } +/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16 +/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. Resulting elements are saturated in case of overflow. +/// +/// \code{.operation} +/// FOR i := 0 to 31 +/// IF __U[i] +/// IF i < 16 +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i]) +/// ELSE +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16]) +/// FI +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction. +/// +/// \param __U +/// A 32-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \param __B +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the +/// (converted) elements from \a __B; higher order elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// zero is taken instead. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( @@ -381,207 +2230,1161 @@ _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) { (__v32qi)(__m256i)_mm256_setzero_si256()); } +/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point +/// elements to a 128-bit vector containing FP16 elements. The conversion is exact. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTHF82PH instruction. +/// +/// \param __A +/// A 128-bit vector of [16 x hf8]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvthf8_ph(__m128i __A) { return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask( (__v16qi)__A, (__v8hf)(__m128h)_mm_undefined_ph(), (__mmask8)-1); } +/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point +/// elements to a 128-bit vector containing FP16 elements. The conversion is +/// exact. Merging mask \a __U is used to determine if given element should be +/// taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i]) +/// ELSE +/// dst.fp16[i] := __W.fp16[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTHF82PH instruction. +/// +/// \param __W +/// A 128-bit vector of [8 x fp16]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [16 x hf8]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_mask_cvthf8_ph(__m128h __W, __mmask8 __U, __m128i __A) { return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask( (__v16qi)__A, (__v8hf)(__m128h)__W, (__mmask8)__U); } +/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point +/// elements to a 128-bit vector containing FP16 elements. The conversion is +/// exact. Zeroing mask \a __U is used to determine if given element should be +/// zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i]) +/// ELSE +/// dst.fp16[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTHF82PH instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [16 x hf8]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// zero is taken instead. static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_maskz_cvthf8_ph(__mmask8 __U, __m128i __A) { return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask( (__v16qi)__A, (__v8hf)(__m128h)_mm_setzero_ph(), (__mmask8)__U); } +/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point +/// elements to a 256-bit vector containing FP16 elements. The conversion is exact. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i]) +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTHF82PH instruction. +/// +/// \param __A +/// A 256-bit vector of [32 x hf8]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvthf8_ph(__m128i __A) { return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask( (__v16qi)__A, (__v16hf)(__m256h)_mm256_undefined_ph(), (__mmask16)-1); } +/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point +/// elements to a 256-bit vector containing FP16 elements. The conversion is +/// exact. Merging mask \a __U is used to determine if given element should be +/// taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i]) +/// ELSE +/// dst.fp16[i] := __W.fp16[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTHF82PH instruction. +/// +/// \param __W +/// A 256-bit vector of [16 x fp16]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [32 x hf8]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_mask_cvthf8_ph(__m256h __W, __mmask16 __U, __m128i __A) { return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask( (__v16qi)__A, (__v16hf)(__m256h)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point +/// elements to a 256-bit vector containing FP16 elements. The conversion is +/// exact. Zeroing mask \a __U is used to determine if given element should be +/// zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i]) +/// ELSE +/// dst.fp16[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:256] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTHF82PH instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [32 x hf8]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// zero is taken instead. static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_maskz_cvthf8_ph(__mmask16 __U, __m128i __A) { return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask( (__v16qi)__A, (__v16hf)(__m256h)_mm256_setzero_ph(), (__mmask16)__U); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of +/// resulting vector are zeroed. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the (converted) +/// elements from \a __A; upper elements are zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask( (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of +/// resulting vector are zeroed. Merging mask \a __U is used to determine if +/// given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i]) +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// (converted) elements from \a __A; upper elements are zeroed. If +/// corresponding mask bit is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask( (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of +/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if +/// given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i]) +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// (converted) elements from \a __A; upper elements are zeroed. If +/// corresponding mask bit is not set, then element is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask( (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U); } -static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtph_bf8(__m256h __A) { +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the (converted) +/// elements from \a __A. +static __inline__ __m128i __DEFAULT_FN_ATTRS256 +_mm256_cvtph_bf8(__m256h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask( (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1); } +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Merging mask \a __U is +/// used to determine if given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i]) +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the +/// (converted) elements from \a __A. If +/// corresponding mask bit is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask( (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Zeroing mask \a __U is +/// used to determine if given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i]) +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// then element is zeroed instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask( (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of +/// resulting vector are zeroed. Results are saturated. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the (converted) +/// elements from \a __A; upper elements are zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask( (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of +/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is +/// used to determine if given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i]) +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// (converted) elements from \a __A; upper elements are zeroed. If +/// corresponding mask bit is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask( (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of +/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is +/// used to determine if given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i]) +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the +/// (converted) elements from \a __A; upper elements are zeroed. If +/// corresponding mask bit is not set, then element is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask( (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U); } -static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtsph_bf8(__m256h __A) { +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the (converted) +/// elements from \a __A. +static __inline__ __m128i __DEFAULT_FN_ATTRS256 +_mm256_cvtsph_bf8(__m256h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask( (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1); } +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i]) +/// ELSE +/// dst.bf8[i] := __W.bf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x bf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the +/// (converted) elements from \a __A. If +/// corresponding mask bit is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask( (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i]) +/// ELSE +/// dst.bf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// then element is zeroed instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) { return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask( (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of +/// resulting vector are zeroed. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the (converted) +/// elements from \a __A; upper elements are zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask( (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of +/// resulting vector are zeroed. Merging mask \a __U is used to determine if +/// given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i]) +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// (converted) elements from \a __A; upper elements are zeroed. If +/// corresponding mask bit is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask( (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of +/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if +/// given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i]) +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// (converted) elements from \a __A; upper elements are zeroed. If +/// corresponding mask bit is not set, then element is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask( (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U); } -static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtph_hf8(__m256h __A) { +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the (converted) +/// elements from \a __A. +static __inline__ __m128i __DEFAULT_FN_ATTRS256 +_mm256_cvtph_hf8(__m256h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask( (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1); } +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Merging mask \a __U is +/// used to determine if given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i]) +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the +/// (converted) elements from \a __A. If +/// corresponding mask bit is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask( (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Zeroing mask \a __U is +/// used to determine if given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i]) +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// then element is zeroed instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask( (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of +/// resulting vector are zeroed. Results are saturated. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction. +/// +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the (converted) +/// elements from \a __A; upper elements are zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask( (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of +/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is +/// used to determine if given element should be taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i]) +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// (converted) elements from \a __A; upper elements are zeroed. If +/// corresponding mask bit is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask( (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U); } +/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of +/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is +/// used to determine if given element should be zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i]) +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:64] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the +/// (converted) elements from \a __A; upper elements are zeroed. If +/// corresponding mask bit is not set, then element is zeroed. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask( (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U); } -static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtsph_hf8(__m256h __A) { +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i]) +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction. +/// +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the (converted) +/// elements from \a __A. +static __inline__ __m128i __DEFAULT_FN_ATTRS256 +_mm256_cvtsph_hf8(__m256h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask( (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1); } +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated. +/// Merging mask \a __U is used to determine if given element should be taken +/// from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i]) +/// ELSE +/// dst.hf8[i] := __W.hf8[i] +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction. +/// +/// \param __W +/// A 128-bit vector of [16 x hf8]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [8 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the +/// (converted) elements from \a __A. If +/// corresponding mask bit is not set, then element from \a __W is taken instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask( (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U); } +/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements +/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated. +/// Zeroing mask \a __U is used to determine if given element should be zeroed +/// instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i]) +/// ELSE +/// dst.hf8[i] := 0 +/// FI +/// ENDFOR +/// +/// dst[MAX:128] := 0 +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [16 x fp16]. +/// \returns +/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, +/// then element is zeroed instead. static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) { return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask( (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U); } +/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point +/// elements to a 128-bit vector containing FP16 elements. The conversion is exact. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic does not correspond to a single instruction. +/// +/// \param __A +/// A 128-bit vector of [16 x bf8]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) { return _mm_castsi128_ph(_mm_slli_epi16(_mm_cvtepi8_epi16(__A), 8)); } +/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point +/// elements to a 128-bit vector containing FP16 elements. The conversion is +/// exact. Merging mask \a __U is used to determine if given element should be +/// taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i]) +/// ELSE +/// dst.fp16[i] := __W.fp16[i] +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic does not correspond to a single instruction. +/// +/// \param __W +/// A 128-bit vector of [8 x fp16]. +/// \param __U +/// A 8-bit merging mask. +/// \param __A +/// A 128-bit vector of [16 x bf8]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m128h __DEFAULT_FN_ATTRS128 -_mm_mask_cvtbf8_ph(__m128h __S, __mmask8 __U, __m128i __A) { +_mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) { return _mm_castsi128_ph( - _mm_mask_slli_epi16((__m128i)__S, __U, _mm_cvtepi8_epi16(__A), 8)); -} - + _mm_mask_slli_epi16((__m128i)__W, __U, _mm_cvtepi8_epi16(__A), 8)); +} + +/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point +/// elements to a 128-bit vector containing FP16 elements. The conversion is +/// exact. Zeroing mask \a __U is used to determine if given element should be +/// zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 7 +/// IF __U[i] +/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i]) +/// ELSE +/// dst.fp16[i] := 0 +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic does not correspond to a single instruction. +/// +/// \param __U +/// A 8-bit zeroing mask. +/// \param __A +/// A 128-bit vector of [16 x bf8]. +/// \returns +/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// zero is taken instead. static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) { return _mm_castsi128_ph(_mm_slli_epi16(_mm_maskz_cvtepi8_epi16(__U, __A), 8)); } +/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point +/// elements to a 256-bit vector containing FP16 elements. The conversion is exact. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic does not correspond to a single instruction. +/// +/// \param __A +/// A 256-bit vector of [32 x bf8]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) { return _mm256_castsi256_ph(_mm256_slli_epi16(_mm256_cvtepi8_epi16(__A), 8)); } +/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point +/// elements to a 256-bit vector containing FP16 elements. The conversion is +/// exact. Merging mask \a __U is used to determine if given element should be +/// taken from \a __W instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i]) +/// ELSE +/// dst.fp16[i] := __W.fp16[i] +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic does not correspond to a single instruction. +/// +/// \param __W +/// A 256-bit vector of [16 x fp16]. +/// \param __U +/// A 16-bit merging mask. +/// \param __A +/// A 256-bit vector of [32 x bf8]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// element from \a __W is taken instead. static __inline__ __m256h __DEFAULT_FN_ATTRS256 -_mm256_mask_cvtbf8_ph(__m256h __S, __mmask16 __U, __m128i __A) { +_mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) { return _mm256_castsi256_ph( - _mm256_mask_slli_epi16((__m256i)__S, __U, _mm256_cvtepi8_epi16(__A), 8)); -} - + _mm256_mask_slli_epi16((__m256i)__W, __U, _mm256_cvtepi8_epi16(__A), 8)); +} + +/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point +/// elements to a 256-bit vector containing FP16 elements. The conversion is +/// exact. Zeroing mask \a __U is used to determine if given element should be +/// zeroed instead. +/// +/// \code{.operation} +/// FOR i := 0 to 15 +/// IF __U[i] +/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i]) +/// ELSE +/// dst.fp16[i] := 0 +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic does not correspond to a single instruction. +/// +/// \param __U +/// A 16-bit zeroing mask. +/// \param __A +/// A 256-bit vector of [32 x bf8]. +/// \returns +/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the +/// (converted) elements from \a __A. If corresponding mask bit is not set, then +/// zero is taken instead. static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_maskz_cvtbf8_ph(__mmask16 __U, __m128i __A) { return _mm256_castsi256_ph( _mm256_slli_epi16(_mm256_maskz_cvtepi8_epi16(__U, __A), 8)); } +// clang-format on + #undef __DEFAULT_FN_ATTRS128 #undef __DEFAULT_FN_ATTRS256