Skip to content

[RISCV] Support [mh]edelegh CSRs #121634

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 8 commits into from
Feb 16, 2025
Merged

[RISCV] Support [mh]edelegh CSRs #121634

Show file tree
Hide file tree
Changes from 3 commits
Commits
Show all changes
8 commits
Select commit Hold shift + click to select a range
bcdf964
Update RISCVSystemOperands.td
dong-miao Jan 4, 2025
30e3fbe
Update rv32-hypervisor-csr-names.s
dong-miao Jan 4, 2025
e41e745
Update rv32-machine-csr-names.s
dong-miao Jan 4, 2025
ea2c1af
Update RISCVSystemOperands.td
dong-miao Jan 5, 2025
6b074f3
Update rv32-only-csr-names.s
dong-miao Jan 5, 2025
f77d8e3
Update RISCVSystemOperands.td
dong-miao Jan 5, 2025
58a1fe2
Merge branch 'main' into main
dong-miao Jan 13, 2025
17b994b
Merge branch 'main' into main
dong-miao Feb 12, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSystemOperands.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
def : SysReg<"hvip", 0x645>;
def : SysReg<"htinst", 0x64A>;
def : SysReg<"hgeip", 0xE12>;
def : SysReg<"hedelegh", 0x612>;
Copy link
Collaborator

@topperc topperc Jan 4, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Need let isRV32Only = 1 in

Should this be in the "Hypervisor Trap Setup" section with hedeleg.

Copy link
Collaborator

@topperc topperc Jan 5, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Still need to move to the "Hypervisor Trap Setup" section instead of "Hypervisor Trap Handling". It belongs in the same group as "hedeleg"


//===----------------------------------------------------------------------===//
// Hypervisor Configuration
Expand Down Expand Up @@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
def : SysReg<"mip", 0x344>;
def : SysReg<"mtinst", 0x34A>;
def : SysReg<"mtval2", 0x34B>;
def : SysReg<"medelegh", 0x312>;

//===----------------------------------------------------------------------===//
// Machine Configuration
Expand Down
18 changes: 18 additions & 0 deletions llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
csrrs t1, vsiph, zero
# uimm12
csrrs t2, 0x254, zero

##################################
# Hypervisor Trap Setup
##################################

# hedelegh
# name
# CHECK-INST: csrrs t1, hedelegh, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
# CHECK-INST-ALIAS: csrr t1, hedelegh
# uimm12
# CHECK-INST: csrrs t2, hedelegh, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
# CHECK-INST-ALIAS: csrr t2, hedelegh
# name
csrrs t1, hedelegh, zero
# uimm12
csrrs t2, 0x612, zero
14 changes: 14 additions & 0 deletions llvm/test/MC/RISCV/rv32-machine-csr-names.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
# uimm12
csrrs t2, 0x310, zero

# medelegh
# name
# CHECK-INST: csrrs t1, medelegh, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
# CHECK-INST-ALIAS: csrr t1, medelegh
# uimm12
# CHECK-INST: csrrs t2, medelegh, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
# CHECK-INST-ALIAS: csrr t2, medelegh
# name
csrrs t1, medelegh, zero
# uimm12
csrrs t2, 0x312, zero

#########################
# Machine Configuration
#########################
Expand Down
Loading