From 8c7a4f421e0822e72df3147bfab41fe18f550c2a Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Tue, 7 Jan 2025 15:39:43 +0800 Subject: [PATCH 1/2] [InstCombine] Add pre-commit tests. NFC. --- .../Transforms/InstCombine/select-divrem.ll | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/select-divrem.ll b/llvm/test/Transforms/InstCombine/select-divrem.ll index a674f9c64b200..08a6d7662f77b 100644 --- a/llvm/test/Transforms/InstCombine/select-divrem.ll +++ b/llvm/test/Transforms/InstCombine/select-divrem.ll @@ -322,6 +322,23 @@ define i8 @rem_euclid_non_const_pow2(i8 %0, i8 %1) { ret i8 %sel } +define i8 @rem_euclid_non_const_pow2_commuted(i8 %0, i8 %1) { +; CHECK-LABEL: @rem_euclid_non_const_pow2_commuted( +; CHECK-NEXT: [[POW2:%.*]] = shl nuw i8 1, [[TMP0:%.*]] +; CHECK-NEXT: [[REM:%.*]] = srem i8 [[TMP1:%.*]], [[POW2]] +; CHECK-NEXT: [[COND:%.*]] = icmp slt i8 [[REM]], 0 +; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], i8 [[POW2]], i8 0 +; CHECK-NEXT: [[SEL:%.*]] = add i8 [[REM]], [[ADD]] +; CHECK-NEXT: ret i8 [[SEL]] +; + %pow2 = shl i8 1, %0 + %rem = srem i8 %1, %pow2 + %cond = icmp slt i8 %rem, 0 + %add = add i8 %pow2, %rem + %sel = select i1 %cond, i8 %add, i8 %rem + ret i8 %sel +} + define i32 @rem_euclid_pow2_true_arm_folded(i32 %n) { ; CHECK-LABEL: @rem_euclid_pow2_true_arm_folded( ; CHECK-NEXT: [[RES:%.*]] = and i32 [[N:%.*]], 1 From d5fb515d35755ebd2e7778885f52dd51510bf838 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Tue, 7 Jan 2025 15:47:52 +0800 Subject: [PATCH 2/2] [InstCombine] Handle commuted patterns in `foldSelectWithSRem` --- llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | 4 ++-- llvm/test/Transforms/InstCombine/select-divrem.ll | 8 +++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 7fd91c72a2fb0..c58a63483a717 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -2823,9 +2823,9 @@ static Instruction *foldSelectWithSRem(SelectInst &SI, InstCombinerImpl &IC, // %cnd = icmp slt i32 %rem, 0 // %add = add i32 %rem, %n // %sel = select i1 %cnd, i32 %add, i32 %rem - if (match(TrueVal, m_Add(m_Specific(RemRes), m_Value(Remainder))) && + if (match(TrueVal, m_c_Add(m_Specific(RemRes), m_Value(Remainder))) && match(RemRes, m_SRem(m_Value(Op), m_Specific(Remainder))) && - IC.isKnownToBeAPowerOfTwo(Remainder, /*OrZero*/ true) && + IC.isKnownToBeAPowerOfTwo(Remainder, /*OrZero=*/true) && FalseVal == RemRes) return FoldToBitwiseAnd(Remainder); diff --git a/llvm/test/Transforms/InstCombine/select-divrem.ll b/llvm/test/Transforms/InstCombine/select-divrem.ll index 08a6d7662f77b..7dff78e3057e2 100644 --- a/llvm/test/Transforms/InstCombine/select-divrem.ll +++ b/llvm/test/Transforms/InstCombine/select-divrem.ll @@ -324,11 +324,9 @@ define i8 @rem_euclid_non_const_pow2(i8 %0, i8 %1) { define i8 @rem_euclid_non_const_pow2_commuted(i8 %0, i8 %1) { ; CHECK-LABEL: @rem_euclid_non_const_pow2_commuted( -; CHECK-NEXT: [[POW2:%.*]] = shl nuw i8 1, [[TMP0:%.*]] -; CHECK-NEXT: [[REM:%.*]] = srem i8 [[TMP1:%.*]], [[POW2]] -; CHECK-NEXT: [[COND:%.*]] = icmp slt i8 [[REM]], 0 -; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], i8 [[POW2]], i8 0 -; CHECK-NEXT: [[SEL:%.*]] = add i8 [[REM]], [[ADD]] +; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[TMP0:%.*]] +; CHECK-NEXT: [[TMP3:%.*]] = xor i8 [[NOTMASK]], -1 +; CHECK-NEXT: [[SEL:%.*]] = and i8 [[TMP1:%.*]], [[TMP3]] ; CHECK-NEXT: ret i8 [[SEL]] ; %pow2 = shl i8 1, %0