From 34173d62dd16cb4e8e7ac404b3772e90899e285a Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Tue, 7 Jan 2025 14:36:32 -0800 Subject: [PATCH] [RISCV] Update the latency of MUL and CPOP in SiFive P400 scheduling model According to llvm-exegesis, they should have around 2 cycles of latency on P400 cores. --- llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 2 +- .../llvm-mca/RISCV/SiFiveP400/mul-cpop.s | 60 +++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td index a86c255f0820e..396cbe2c476c6 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td @@ -182,7 +182,7 @@ def P400WriteCMOV : SchedWriteRes<[SiFiveP400Branch, SiFiveP400IEXQ1]> { } def : InstRW<[P400WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>; -let Latency = 3 in { +let Latency = 2 in { // Integer multiplication def : WriteRes; def : WriteRes; diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s new file mode 100644 index 0000000000000..5f7a1d1dce09b --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s @@ -0,0 +1,60 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s + +mul s6, s6, s7 + +mulw s4, s4, a2 + +cpop t1, t1 + +cpopw t2, t2 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 4 +# CHECK-NEXT: Total Cycles: 8 +# CHECK-NEXT: Total uOps: 4 + +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 2 1.00 mul s6, s6, s7 +# CHECK-NEXT: 1 2 1.00 mulw s4, s4, a2 +# CHECK-NEXT: 1 2 1.00 cpop t1, t1 +# CHECK-NEXT: 1 2 1.00 cpopw t2, t2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFiveP400Div +# CHECK-NEXT: [1] - SiFiveP400FEXQ0 +# CHECK-NEXT: [2] - SiFiveP400FloatDiv +# CHECK-NEXT: [3] - SiFiveP400IEXQ0 +# CHECK-NEXT: [4] - SiFiveP400IEXQ1 +# CHECK-NEXT: [5] - SiFiveP400IEXQ2 +# CHECK-NEXT: [6] - SiFiveP400Load +# CHECK-NEXT: [7] - SiFiveP400Store +# CHECK-NEXT: [8] - SiFiveP400VDiv +# CHECK-NEXT: [9] - SiFiveP400VEXQ0 +# CHECK-NEXT: [10] - SiFiveP400VFloatDiv +# CHECK-NEXT: [11] - SiFiveP400VLD +# CHECK-NEXT: [12] - SiFiveP400VST + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] +# CHECK-NEXT: - - - - - 4.00 - - - - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: +# CHECK-NEXT: - - - - - 1.00 - - - - - - - mul s6, s6, s7 +# CHECK-NEXT: - - - - - 1.00 - - - - - - - mulw s4, s4, a2 +# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpop t1, t1 +# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpopw t2, t2