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[RISCV][VLOPT] Add floating point widening and narrowing bf16 convert support #122353

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merged 2 commits into from
Jan 13, 2025
Merged

[RISCV][VLOPT] Add floating point widening and narrowing bf16 convert support #122353

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7dd2510
[RISCV][VLOPT] Add floating point widening and narrowing convert support
michaelmaitland Jan 9, 2025
68886b9
fixup! fix tests
michaelmaitland Jan 9, 2025
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6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -551,6 +551,7 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
case RISCV::VFWCVT_F_XU_V:
case RISCV::VFWCVT_F_X_V:
case RISCV::VFWCVT_F_F_V:
case RISCV::VFWCVTBF16_F_F_V:
return IsMODef ? MILog2SEW + 1 : MILog2SEW;

// Def and Op1 uses EEW=2*SEW. Op2 uses EEW=SEW.
Expand Down Expand Up @@ -607,7 +608,8 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
case RISCV::VFNCVT_F_XU_W:
case RISCV::VFNCVT_F_X_W:
case RISCV::VFNCVT_F_F_W:
case RISCV::VFNCVT_ROD_F_F_W: {
case RISCV::VFNCVT_ROD_F_F_W:
case RISCV::VFNCVTBF16_F_F_W: {
bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
bool TwoTimes = IsOp1;
return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
Expand Down Expand Up @@ -1045,6 +1047,7 @@ static bool isSupportedInstr(const MachineInstr &MI) {
case RISCV::VFWCVT_F_XU_V:
case RISCV::VFWCVT_F_X_V:
case RISCV::VFWCVT_F_F_V:
case RISCV::VFWCVTBF16_F_F_V:
// Narrowing Floating-Point/Integer Type-Convert Instructions
case RISCV::VFNCVT_XU_F_W:
case RISCV::VFNCVT_X_F_W:
Expand All @@ -1054,6 +1057,7 @@ static bool isSupportedInstr(const MachineInstr &MI) {
case RISCV::VFNCVT_F_X_W:
case RISCV::VFNCVT_F_F_W:
case RISCV::VFNCVT_ROD_F_F_W:
case RISCV::VFNCVTBF16_F_F_W:
return true;
}

Expand Down
44 changes: 14 additions & 30 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -32,12 +32,11 @@ define void @fadd_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v12, v10
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -167,12 +166,11 @@ define void @fsub_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v12, v10
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -302,12 +300,11 @@ define void @fmul_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v12, v10
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -437,12 +434,11 @@ define void @fdiv_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v12, v10
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -1196,9 +1192,7 @@ define void @copysign_neg_trunc_v3bf16_v3f32(ptr %x, ptr %y) {
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addi a2, a1, -1
; CHECK-NEXT: vand.vx v8, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v9
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
; CHECK-NEXT: vxor.vx v9, v10, a1
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vor.vv v8, v8, v9
Expand Down Expand Up @@ -2263,13 +2257,12 @@ define void @fadd_vf_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.x.w a1, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v10, v12
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -2404,13 +2397,12 @@ define void @fadd_fv_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.x.w a1, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v12, v10
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -2545,13 +2537,12 @@ define void @fsub_vf_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.x.w a1, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v10, v12
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -2686,13 +2677,12 @@ define void @fsub_fv_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.x.w a1, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v12, v10
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -2827,13 +2817,12 @@ define void @fmul_vf_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.x.w a1, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v12
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -2968,13 +2957,12 @@ define void @fmul_fv_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.x.w a1, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v12, v10
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -3109,13 +3097,12 @@ define void @fdiv_vf_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.x.w a1, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v10, v12
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -3250,13 +3237,12 @@ define void @fdiv_fv_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.x.w a1, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v12, v10
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -4908,7 +4894,6 @@ define void @fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vle16.v v10, (a2)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
Expand All @@ -4919,7 +4904,7 @@ define void @fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v12
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -5082,7 +5067,6 @@ define void @fmsub_fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vle16.v v10, (a2)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
Expand All @@ -5093,7 +5077,7 @@ define void @fmsub_fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
Expand Down
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