diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td index 14e34c9e00ec6..102f654e1a884 100644 --- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td @@ -870,25 +870,40 @@ class VOPC_Class_Profile sched, ValueType src0VT, ValueType multiclass VOPC_Class_Profile_t16 sched> { def NAME : VOPC_Class_Profile; - def _t16 : VOPC_Class_Profile { + def _t16 : VOPC_Class_Profile_Base { let IsTrue16 = 1; let IsRealTrue16 = 1; - let Src1RC32 = getVregSrcForVT.ret; - let Src1RC64 = VSrc_b32; - let Src0DPP = getVregSrcForVT.ret; - let Src1DPP = getVregSrcForVT.ret; - let Src2DPP = getVregSrcForVT.ret; - let Src0ModDPP = getSrcModDPP_t16.ret; - let Src1ModDPP = getSrcModDPP_t16.ret; - let Src2ModDPP = getSrcModDPP_t16.ret; + let HasOpSel = 1; + let HasModifiers = 1; // All instructions at least have OpSel + let DstRC = getVALUDstForVT.ret; + let Src0RC32 = getVOPSrc0ForVT.ret; + let Src1RC32 = getVregSrcForVT.ret; + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; + let Src0ModDPP = getSrcModDPP_t16.ret; + let Src1ModDPP = getSrcModDPP_t16.ret; + let Src2ModDPP = getSrcModDPP_t16.ret; + let Src0VOP3DPP = VGPRSrc_16; + let Src1VOP3DPP = getVOP3DPPSrcForVT.ret; + let Src2VOP3DPP = getVOP3DPPSrcForVT.ret; + + let DstRC64 = getVALUDstForVT.ret; + let Src0RC64 = getVOP3SrcForVT.ret; + let Src1RC64 = getVOP3SrcForVT.ret; + let Src2RC64 = getVOP3SrcForVT.ret; + let Src0Mod = getSrc0Mod.ret; + let Src1Mod = getSrcMod.ret; + let Src2Mod = getSrcMod.ret; + let Src0ModVOP3DPP = getSrc0ModVOP3DPP.ret; + let Src1ModVOP3DPP = getSrcModVOP3DPP.ret; + let Src2ModVOP3DPP = getSrcModVOP3DPP.ret; } def _fake16 : VOPC_Class_Profile_Base { let IsTrue16 = 1; let DstRC = getVALUDstForVT_fake16.ret; - let DstRC64 = getVALUDstForVT.ret; let Src0RC32 = getVOPSrc0ForVT.ret; let Src1RC32 = getVregSrcForVT.ret; - let Src1RC64 = VSrc_b32; let Src0DPP = getVregSrcForVT.ret; let Src1DPP = getVregSrcForVT.ret; let Src2DPP = getVregSrcForVT.ret; @@ -898,6 +913,14 @@ multiclass VOPC_Class_Profile_t16 sched> { let Src0VOP3DPP = VGPRSrc_32; let Src1VOP3DPP = getVOP3DPPSrcForVT.ret; let Src2VOP3DPP = getVOP3DPPSrcForVT.ret; + + let DstRC64 = getVALUDstForVT.ret; + let Src0RC64 = getVOP3SrcForVT.ret; + let Src1RC64 = getVOP3SrcForVT.ret; + let Src2RC64 = getVOP3SrcForVT.ret; + let Src0Mod = getSrc0Mod.ret; + let Src1Mod = getSrcMod.ret; + let Src2Mod = getSrcMod.ret; let Src0ModVOP3DPP = getSrc0ModVOP3DPP.ret; let Src1ModVOP3DPP = getSrcModVOP3DPP.ret; let Src2ModVOP3DPP = getSrcModVOP3DPP.ret; @@ -1843,7 +1866,7 @@ defm V_CMP_NE_U64 : VOPC_Real_gfx11_gfx12<0x05d>; defm V_CMP_GE_U64 : VOPC_Real_gfx11_gfx12<0x05e>; defm V_CMP_T_U64 : VOPC_Real_gfx11<0x05f>; -defm V_CMP_CLASS_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x07d, "v_cmp_class_f16">; +defm V_CMP_CLASS_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x07d, "v_cmp_class_f16">; defm V_CMP_CLASS_F32 : VOPC_Real_gfx11_gfx12<0x07e>; defm V_CMP_CLASS_F64 : VOPC_Real_gfx11_gfx12<0x07f>; diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s index 798616cef6639..a3a60d210a6fe 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s @@ -4,112 +4,127 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_mirror -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_mirror +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_half_mirror -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_half_mirror +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:1 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shl:1 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:15 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shl:15 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:1 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shr:1 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:15 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shr:15 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_ror:1 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_ror:1 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s105, v1, v2 row_ror:15 -// W32: v_cmp_class_f16_e64_dpp s105, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_cmp_class_f16_e64_dpp s105, v1.l, v2.l row_ror:15 +// W32: v_cmp_class_f16_e64_dpp s105, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W32: v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +v_cmp_class_f16_e64_dpp vcc_hi, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_class_f16_e64_dpp vcc_hi, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W32: v_cmp_class_f16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] +v_cmp_class_f16_e64_dpp ttmp15, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_class_f16_e64_dpp ttmp15, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] +v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// GFX11: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30] +v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30] + +v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp ttmp15, v1.h, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_class_f16_e64_dpp ttmp15, v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30] v_cmp_class_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] // W32: v_cmp_class_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s index 0aa37303d6248..1bf4dc85b3bc6 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s @@ -4,44 +4,55 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp vcc_hi, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_hi, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W32: v_cmp_class_f16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp ttmp15, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16_e64_dpp ttmp15, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// GFX11: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x01,0x7d,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x01,0x7d,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +v_cmp_class_f16_e64_dpp ttmp15, v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16_e64_dpp ttmp15, v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x08,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x08,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x11,0x7d,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] v_cmp_class_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // W32: v_cmp_class_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s index 573e3be073b34..1923439dd6723 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s @@ -4,20 +4,20 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_e64 s5, v1, v2 -// W32: v_cmp_class_f16_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +v_cmp_class_f16_e64 s5, v1.l, v2.l +// W32: v_cmp_class_f16_e64 s5, v1.l, v2.l ; encoding: [0x05,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s5, v255, v2 -// W32: v_cmp_class_f16_e64 s5, v255, v2 ; encoding: [0x05,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +v_cmp_class_f16_e64 s5, v255.l, v2.l +// W32: v_cmp_class_f16_e64 s5, v255.l, v2.l ; encoding: [0x05,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s5, s1, v2 -// W32: v_cmp_class_f16_e64 s5, s1, v2 ; encoding: [0x05,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +v_cmp_class_f16_e64 s5, s1, v2.l +// W32: v_cmp_class_f16_e64 s5, s1, v2.l ; encoding: [0x05,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s5, s105, v255 -// W32: v_cmp_class_f16_e64 s5, s105, v255 ; encoding: [0x05,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +v_cmp_class_f16_e64 s5, s105, v255.l +// W32: v_cmp_class_f16_e64 s5, s105, v255.l ; encoding: [0x05,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction v_cmp_class_f16_e64 s5, vcc_lo, s2 @@ -60,24 +60,24 @@ v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo // W32: v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo ; encoding: [0x7b,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], v1, 0.5 -// W64: v_cmp_class_f16_e64 s[10:11], v1, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00] -// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction +v_cmp_class_f16_e64 s10, v1.l, 0.5 +// W32: v_cmp_class_f16_e64 s10, v1.l, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], v1, v2 -// W64: v_cmp_class_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +v_cmp_class_f16_e64 s[10:11], v1.l, v2.l +// W64: v_cmp_class_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] // W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], v255, v2 -// W64: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +v_cmp_class_f16_e64 s[10:11], v255.l, v2.l +// W64: v_cmp_class_f16_e64 s[10:11], v255.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] // W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], s1, v2 -// W64: v_cmp_class_f16_e64 s[10:11], s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +v_cmp_class_f16_e64 s[10:11], s1, v2.l +// W64: v_cmp_class_f16_e64 s[10:11], s1, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] // W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], s105, v255 -// W64: v_cmp_class_f16_e64 s[10:11], s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +v_cmp_class_f16_e64 s[10:11], s105, v255.l +// W64: v_cmp_class_f16_e64 s[10:11], s105, v255.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] // W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction v_cmp_class_f16_e64 s[10:11], vcc_lo, s2 @@ -123,6 +123,26 @@ v_cmp_class_f16_e64 ttmp[14:15], src_scc, vcc_lo v_cmp_class_f16_e64 null, -|0xfe0b|, vcc_hi // GFX11: v_cmp_class_f16_e64 null, -|0xfe0b|, vcc_hi ; encoding: [0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00] +v_cmp_class_f16_e64 vcc_lo, 0.5, m0 +// W32: v_cmp_class_f16_e64 vcc_lo, 0.5, m0 ; encoding: [0x6a,0x00,0x7d,0xd4,0xf0,0xfa,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + +v_cmp_class_f16_e64 s5, v255.h, v2.l +// W32: v_cmp_class_f16_e64 s5, v255.h, v2.l ; encoding: [0x05,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + +v_cmp_class_f16_e64 s5, s105, v255.h +// W32: v_cmp_class_f16_e64 s5, s105, v255.h ; encoding: [0x05,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + +v_cmp_class_f16_e64 s[10:11], v255.h, v2.l +// W64: v_cmp_class_f16_e64 s[10:11], v255.h, v2.l ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00] +// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + +v_cmp_class_f16_e64 s[10:11], s105, v255.h +// W64: v_cmp_class_f16_e64 s[10:11], s105, v255.h ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + v_cmp_class_f32_e64 s5, v1, v2 // W32: v_cmp_class_f32_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s index a39c2070e3262..36e32aad105af 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s @@ -4,124 +4,164 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_e32 vcc_lo, v1, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, v1.l, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v127, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, v127.l, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, s1, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, s1, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, s105, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, s105, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, vcc_lo, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, vcc_lo, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, vcc_hi, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, vcc_hi, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, ttmp15, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, ttmp15, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, m0, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, m0, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, exec_lo, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, exec_lo, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, exec_hi, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, exec_hi, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, null, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, null, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, -1, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, -1, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, 0.5, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, 0.5, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, src_scc, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, src_scc, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, 0xfe0b, v127 -// W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +v_cmp_class_f16 vcc_lo, 0xfe0b, v127.l +// W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 -// W64: v_cmp_class_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] +v_cmp_class_f16 vcc, v1.l, v2.l +// W64: v_cmp_class_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v127, v2 -// W64: v_cmp_class_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] +v_cmp_class_f16 vcc, v127.l, v2.l +// W64: v_cmp_class_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, s1, v2 -// W64: v_cmp_class_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, s1, v2.l +// W64: v_cmp_class_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, s105, v2 -// W64: v_cmp_class_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, s105, v2.l +// W64: v_cmp_class_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, vcc_lo, v2 -// W64: v_cmp_class_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, vcc_lo, v2.l +// W64: v_cmp_class_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, vcc_hi, v2 -// W64: v_cmp_class_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, vcc_hi, v2.l +// W64: v_cmp_class_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, ttmp15, v2 -// W64: v_cmp_class_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, ttmp15, v2.l +// W64: v_cmp_class_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, m0, v2 -// W64: v_cmp_class_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, m0, v2.l +// W64: v_cmp_class_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, exec_lo, v2 -// W64: v_cmp_class_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, exec_lo, v2.l +// W64: v_cmp_class_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, exec_hi, v2 -// W64: v_cmp_class_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, exec_hi, v2.l +// W64: v_cmp_class_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, null, v2 -// W64: v_cmp_class_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, null, v2.l +// W64: v_cmp_class_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, -1, v2 -// W64: v_cmp_class_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, -1, v2.l +// W64: v_cmp_class_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, 0.5, v2 -// W64: v_cmp_class_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, 0.5, v2.l +// W64: v_cmp_class_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, src_scc, v2 -// W64: v_cmp_class_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, src_scc, v2.l +// W64: v_cmp_class_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, 0xfe0b, v127 -// W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +v_cmp_class_f16 vcc, 0xfe0b, v127.l +// W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.h, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.h, v2.l +// W64: v_cmp_class_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v127.h, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v127.h, v2.l +// W64: v_cmp_class_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, 0.5, v127.l +// W32: v_cmp_class_f16_e32 vcc_lo, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfa,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, 0.5, v127.l +// W64: v_cmp_class_f16_e32 vcc, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfa,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, src_scc, v2.h +// W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, src_scc, v2.h +// W64: v_cmp_class_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, 0xfe0b, v127.h +// W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, 0xfe0b, v127.h +// W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_class_f32 vcc_lo, v1, v2 diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s index fdaa9a990cb9b..4499545365ed0 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s @@ -4,116 +4,220 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_dpp vcc_lo, v1, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] -// W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_mirror -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// W32: v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30] +v_cmp_class_f16 vcc_lo, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// W32: v_cmp_class_f16 vcc_lo, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] -// W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] +// W64: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_mirror -// W64: v_cmp_class_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_mirror +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_half_mirror -// W64: v_cmp_class_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_shl:1 -// W64: v_cmp_class_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_shl:15 -// W64: v_cmp_class_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_shr:1 -// W64: v_cmp_class_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_shr:15 -// W64: v_cmp_class_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_ror:1 -// W64: v_cmp_class_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_ror:15 -// W64: v_cmp_class_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W64: v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W64: v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +v_cmp_class_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W64: v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13] +v_cmp_class_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// W64: v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30] +v_cmp_class_f16 vcc, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// W64: v_cmp_class_f16 vcc, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_class_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_class_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_class_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_class_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: v_cmp_class_f16 vcc_lo, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x35,0x30] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: v_cmp_class_f16 vcc, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x35,0x30] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_class_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s index 97ad419a79ca8..b2d5ab91b1946 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s @@ -4,28 +4,52 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// W32: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// W32: v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W64: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// W64: v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// W64: v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_class_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: v_cmp_class_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: v_cmp_class_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_class_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s index c48bff454deed..16aec6f0d7dcb 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s @@ -1,62 +1,119 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s -v_cmp_class_f16_e32 vcc, v1, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc, v1.h, v255.h +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v127, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc, v1.l, v255.l +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.h, v255.h +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.l, v255.l +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.h, v2.h +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.l, v2.l +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, vcc_hi, v255.h +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, vcc_hi, v255.l +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, vcc_lo, v255.h +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, vcc_lo, v255.l +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] +v_cmp_class_f16_e32 vcc_lo, v127.h, v255.h // GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0] +v_cmp_class_f16_e32 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] // GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v128, v2 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v127.l, v255.l +// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, vcc_hi, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, vcc_lo, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v128.h, v2.h +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v127, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:40: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:40: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v128.l, v2.l +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v128, v2 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:38: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:38: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255.h +// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255.l +// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255.h +// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255.l +// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction v_cmp_eq_f16_e32 vcc, v1, v255 // GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s index dc0bf7663ac17..ec5a9edcfc19d 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s @@ -1,62 +1,119 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s -v_cmp_class_f16 vcc, v1, v255 -// GFX11: v_cmp_class_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x01,0xff,0x03,0x00] +v_cmp_class_f16 vcc, v1.h, v255.h +// GFX11: v_cmp_class_f16_e64 vcc, v1.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x01,0xff,0x03,0x00] -v_cmp_class_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_cmp_class_f16 vcc, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_cmp_class_f16 vcc, v127, v255 -// GFX11: v_cmp_class_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x7f,0xff,0x03,0x00] +v_cmp_class_f16 vcc, v1.l, v255.l +// GFX11: v_cmp_class_f16_e64 vcc, v1.l, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x01,0xff,0x03,0x00] -v_cmp_class_f16 vcc, v127, v255 -// GFX11: v_cmp_class_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x7f,0xff,0x03,0x00] +v_cmp_class_f16 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_cmp_class_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_cmp_class_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v127.h, v255.h +// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00] -v_cmp_class_f16 vcc, v127, v255 quad_perm:[3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v127.h, v255.h +// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00] -v_cmp_class_f16 vcc, v127, v255 quad_perm:[3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] -v_cmp_class_f16 vcc, v128, v2 -// GFX11: v_cmp_class_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x7d,0xd4,0x80,0x05,0x02,0x00] +v_cmp_class_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] -v_cmp_class_f16 vcc, v128, v2 -// GFX11: v_cmp_class_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x7d,0xd4,0x80,0x05,0x02,0x00] +v_cmp_class_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] -v_cmp_class_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] -v_cmp_class_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v127.l, v255.l +// GFX11: v_cmp_class_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x7f,0xff,0x03,0x00] -v_cmp_class_f16 vcc, v128, v2 quad_perm:[3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v127.l, v255.l +// GFX11: v_cmp_class_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x7f,0xff,0x03,0x00] -v_cmp_class_f16 vcc, v128, v2 quad_perm:[3,2,1,0] -// GFX11: v_cmp_class_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] -v_cmp_class_f16 vcc, vcc_hi, v255 -// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00] +v_cmp_class_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] -v_cmp_class_f16 vcc, vcc_hi, v255 -// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00] +v_cmp_class_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] -v_cmp_class_f16 vcc, vcc_lo, v255 -// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00] +v_cmp_class_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] -v_cmp_class_f16 vcc, vcc_lo, v255 -// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00] +v_cmp_class_f16 vcc, v128.h, v2.h +// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00] + +v_cmp_class_f16 vcc, v128.h, v2.h +// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00] + +v_cmp_class_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] + +v_cmp_class_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] + +v_cmp_class_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] + +v_cmp_class_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] + +v_cmp_class_f16 vcc, v128.l, v2.l +// GFX11: v_cmp_class_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x80,0x05,0x02,0x00] + +v_cmp_class_f16 vcc, v128.l, v2.l +// GFX11: v_cmp_class_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x80,0x05,0x02,0x00] + +v_cmp_class_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] + +v_cmp_class_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] + +v_cmp_class_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] + +v_cmp_class_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] + +v_cmp_class_f16 vcc, vcc_hi, v255.h +// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00] + +v_cmp_class_f16 vcc, vcc_hi, v255.h +// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00] + +v_cmp_class_f16 vcc, vcc_hi, v255.l +// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00] + +v_cmp_class_f16 vcc, vcc_hi, v255.l +// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00] + +v_cmp_class_f16 vcc, vcc_lo, v255.h +// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00] + +v_cmp_class_f16 vcc, vcc_lo, v255.h +// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00] + +v_cmp_class_f16 vcc, vcc_lo, v255.l +// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00] + +v_cmp_class_f16 vcc, vcc_lo, v255.l +// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00] v_cmp_eq_f16 vcc, v1, v255 // GFX11: v_cmp_eq_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s index 177b994d5ad06..2197b27704f72 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s @@ -4,20 +4,20 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_e64 s5, v1, v2 -// W32: v_cmp_class_f16_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +v_cmp_class_f16_e64 s5, v1.l, v2.l +// W32: v_cmp_class_f16_e64 s5, v1.l, v2.l ; encoding: [0x05,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s5, v255, v2 -// W32: v_cmp_class_f16_e64 s5, v255, v2 ; encoding: [0x05,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +v_cmp_class_f16_e64 s5, v255.l, v2.l +// W32: v_cmp_class_f16_e64 s5, v255.l, v2.l ; encoding: [0x05,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s5, s1, v2 -// W32: v_cmp_class_f16_e64 s5, s1, v2 ; encoding: [0x05,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +v_cmp_class_f16_e64 s5, s1, v2.l +// W32: v_cmp_class_f16_e64 s5, s1, v2.l ; encoding: [0x05,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s5, s105, v255 -// W32: v_cmp_class_f16_e64 s5, s105, v255 ; encoding: [0x05,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +v_cmp_class_f16_e64 s5, s105, v255.l +// W32: v_cmp_class_f16_e64 s5, s105, v255.l ; encoding: [0x05,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction v_cmp_class_f16_e64 s5, vcc_lo, s2 @@ -60,21 +60,21 @@ v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo // W32: v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo ; encoding: [0x7b,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], v1, v2 -// W64: v_cmp_class_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +v_cmp_class_f16_e64 s[10:11], v1.l, v2.l +// W64: v_cmp_class_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] // W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], v255, v2 -// W64: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] -// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction +v_cmp_class_f16_e64 s10, v255.l, v2.l +// W32: v_cmp_class_f16_e64 s10, v255.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], s1, v2 -// W64: v_cmp_class_f16_e64 s[10:11], s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +v_cmp_class_f16_e64 s[10:11], s1, v2.l +// W64: v_cmp_class_f16_e64 s[10:11], s1, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] // W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction -v_cmp_class_f16_e64 s[10:11], s105, v255 -// W64: v_cmp_class_f16_e64 s[10:11], s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction +v_cmp_class_f16_e64 s10, s105, v255.l +// W32: v_cmp_class_f16_e64 s10, s105, v255.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction v_cmp_class_f16_e64 s[10:11], vcc_lo, s2 // W64: v_cmp_class_f16_e64 s[10:11], vcc_lo, s2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00] @@ -119,6 +119,26 @@ v_cmp_class_f16_e64 ttmp[14:15], src_scc, vcc_lo v_cmp_class_f16_e64 null, -|0xfe0b|, vcc_hi // GFX12: v_cmp_class_f16_e64 null, -|0xfe0b|, vcc_hi ; encoding: [0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00] +v_cmp_class_f16_e64 s5, v255.h, v2.l +// W32: v_cmp_class_f16_e64 s5, v255.h, v2.l ; encoding: [0x05,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + +v_cmp_class_f16_e64 s5, s105, v255.h +// W32: v_cmp_class_f16_e64 s5, s105, v255.h ; encoding: [0x05,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + +v_cmp_class_f16_e64 s[10:11], v255.h, v2.l +// W64: v_cmp_class_f16_e64 s[10:11], v255.h, v2.l ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00] +// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + +v_cmp_class_f16_e64 s[10:11], s105, v255.h +// W64: v_cmp_class_f16_e64 s[10:11], s105, v255.h ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + +v_cmp_class_f16_e64 vcc_lo, 0.5, m0 +// W32: v_cmp_class_f16_e64 vcc_lo, 0.5, m0 ; encoding: [0x6a,0x00,0x7d,0xd4,0xf0,0xfa,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction + v_cmp_class_f32_e64 s5, v1, v2 // W32: v_cmp_class_f32_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s index 8908f18ac29bb..f75b1b249fe3e 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s @@ -4,128 +4,143 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, s2 quad_perm:[3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s5, v1, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, s2 quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, 2.0 quad_perm:[3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s5, v1, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, 2.0 quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_mirror -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_mirror +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_half_mirror -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_half_mirror +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:1 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shl:1 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:15 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shl:15 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:1 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shr:1 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:15 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shr:15 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, v2 row_ror:1 -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_ror:1 +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s105, v1, v2 row_ror:15 -// W32: v_cmp_class_f16_e64_dpp s105, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_cmp_class_f16_e64_dpp s105, v1.l, v2.l row_ror:15 +// W32: v_cmp_class_f16_e64_dpp s105, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W32: v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +v_cmp_class_f16_e64_dpp vcc_hi, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_class_f16_e64_dpp vcc_hi, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W32: v_cmp_class_f16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] +v_cmp_class_f16_e64_dpp ttmp15, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_class_f16_e64_dpp ttmp15, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, s2 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, s2 quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, 2.0 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, 2.0 quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] +v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// GFX12: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30] +v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30] + +v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30] + +v_cmp_class_f16_e64_dpp ttmp15, v1.h, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_class_f16_e64_dpp ttmp15, v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction v_cmp_class_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] // W32: v_cmp_class_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s index 80ac6aa9af00e..1cdf0f728cac7 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s @@ -4,60 +4,71 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, s2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s5, v1, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7d,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s5, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7d,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s5, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s5, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp vcc_hi, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_hi, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W32: v_cmp_class_f16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp ttmp15, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16_e64_dpp ttmp15, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, s2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[10:11], v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[10:11], v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s[10:11], v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[10:11], v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16_e64_dpp ttmp14, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16_e64_dpp ttmp14, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] +// GFX12: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x01,0x7d,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +v_cmp_class_f16_e64_dpp ttmp15, v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16_e64_dpp ttmp15, v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x08,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction + +v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x08,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction -v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// GFX12: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x01,0x7d,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x11,0x7d,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] v_cmp_class_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // W32: v_cmp_class_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s index 7991231aa68ed..be53815220850 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s @@ -4,124 +4,156 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_e32 vcc_lo, v1, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, v1.l, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v127, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, v127.l, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, s1, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, s1, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, s105, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, s105, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, vcc_lo, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, vcc_lo, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, vcc_hi, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, vcc_hi, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, ttmp15, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, ttmp15, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, m0, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, m0, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, exec_lo, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, exec_lo, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, exec_hi, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, exec_hi, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, null, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, null, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, -1, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, -1, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, 0.5, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, 0.5, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, src_scc, v2 -// W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc_lo, src_scc, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, 0xfe0b, v127 -// W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +v_cmp_class_f16 vcc_lo, 0xfe0b, v127.l +// W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 -// W64: v_cmp_class_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] +v_cmp_class_f16 vcc, v1.l, v2.l +// W64: v_cmp_class_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v127, v2 -// W64: v_cmp_class_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] +v_cmp_class_f16 vcc, v127.l, v2.l +// W64: v_cmp_class_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, s1, v2 -// W64: v_cmp_class_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, s1, v2.l +// W64: v_cmp_class_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, s105, v2 -// W64: v_cmp_class_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, s105, v2.l +// W64: v_cmp_class_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, vcc_lo, v2 -// W64: v_cmp_class_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, vcc_lo, v2.l +// W64: v_cmp_class_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, vcc_hi, v2 -// W64: v_cmp_class_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, vcc_hi, v2.l +// W64: v_cmp_class_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, ttmp15, v2 -// W64: v_cmp_class_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, ttmp15, v2.l +// W64: v_cmp_class_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, m0, v2 -// W64: v_cmp_class_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, m0, v2.l +// W64: v_cmp_class_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, exec_lo, v2 -// W64: v_cmp_class_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, exec_lo, v2.l +// W64: v_cmp_class_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, exec_hi, v2 -// W64: v_cmp_class_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, exec_hi, v2.l +// W64: v_cmp_class_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, null, v2 -// W64: v_cmp_class_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, null, v2.l +// W64: v_cmp_class_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, -1, v2 -// W64: v_cmp_class_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, -1, v2.l +// W64: v_cmp_class_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, 0.5, v2 -// W64: v_cmp_class_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, 0.5, v2.l +// W64: v_cmp_class_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, src_scc, v2 -// W64: v_cmp_class_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] +v_cmp_class_f16 vcc, src_scc, v2.l +// W64: v_cmp_class_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, 0xfe0b, v127 -// W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +v_cmp_class_f16 vcc, 0xfe0b, v127.l +// W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.h, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.h, v2.l +// W64: v_cmp_class_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v127.h, v2.l +// W32: v_cmp_class_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v127.h, v2.l +// W64: v_cmp_class_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, src_scc, v2.h +// W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, src_scc, v2.h +// W64: v_cmp_class_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, 0xfe0b, v127.h +// W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, 0xfe0b, v127.h +// W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_class_f32 vcc_lo, v1, v2 diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s index 54c3df6b139af..cd294deb5c3e8 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s @@ -4,116 +4,212 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_dpp vcc_lo, v1, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] -// W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_mirror -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13] +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// W32: v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30] +v_cmp_class_f16 vcc_lo, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// W32: v_cmp_class_f16 vcc_lo, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] -// W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] +// W64: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_mirror -// W64: v_cmp_class_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_mirror +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_half_mirror -// W64: v_cmp_class_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_shl:1 -// W64: v_cmp_class_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_shl:15 -// W64: v_cmp_class_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_shr:1 -// W64: v_cmp_class_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_shr:15 -// W64: v_cmp_class_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_ror:1 -// W64: v_cmp_class_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_ror:15 -// W64: v_cmp_class_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W64: v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +v_cmp_class_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W64: v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +v_cmp_class_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W64: v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13] +v_cmp_class_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// W64: v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30] +v_cmp_class_f16 vcc, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// W64: v_cmp_class_f16 vcc, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_class_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_class_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: v_cmp_class_f16 vcc_lo, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x35,0x30] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: v_cmp_class_f16 vcc, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x35,0x30] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_class_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s index 7414795639205..347b92a4da119 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s @@ -4,28 +4,44 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// W32: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// W32: v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W64: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// W64: v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// W64: v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_class_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_class_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: v_cmp_class_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_class_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: v_cmp_class_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_class_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s index 8944a76fcc801..890eb81af9226 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s @@ -1,62 +1,119 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=error %s -v_cmp_class_f16_e32 vcc, v1, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc, v1.h, v255.h +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v127, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc, v1.l, v255.l +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.h, v255.h +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.l, v255.l +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.h, v2.h +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.l, v2.l +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, vcc_hi, v255.h +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, vcc_hi, v255.l +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, vcc_lo, v255.h +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc, vcc_lo, v255.l +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] +v_cmp_class_f16_e32 vcc_lo, v127.h, v255.h // GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0] +v_cmp_class_f16_e32 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] // GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v128, v2 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v127.l, v255.l +// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, vcc_hi, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc, vcc_lo, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v128.h, v2.h +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v127, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:40: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:40: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v128.l, v2.l +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v128, v2 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:38: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:38: error: invalid operand for instruction +v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255.h +// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255.l +// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction -v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255.h +// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction + +v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255.l +// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction v_cmp_eq_f16_e32 vcc, v1, v255 // GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s index d37859f2802b8..c53bdaa98a9c9 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s @@ -1,84 +1,160 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefix=W32 %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefix=W64 %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 %s 2>&1 > /dev/null | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 %s 2>&1 > /dev/null | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s -v_cmp_class_f16 vcc, v1, v255 -// W64: v_cmp_class_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x01,0xff,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc, v1.h, v255.h +// W64: v_cmp_class_f16_e64 vcc, v1.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x01,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, v1, v255 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, v127, v255 -// W64: v_cmp_class_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x7f,0xff,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc, v1.l, v255.l +// W64: v_cmp_class_f16_e64 vcc, v1.l, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x01,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, v127, v255 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, v128, v2 -// W64: v_cmp_class_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x7d,0xd4,0x80,0x05,0x02,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc, v127.h, v255.h +// W64: v_cmp_class_f16_e64 vcc, v127.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +v_cmp_class_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, v128, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_class_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +v_cmp_class_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, vcc_hi, v255 -// W64: v_cmp_class_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc, v127.l, v255.l +// W64: v_cmp_class_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x7f,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc, vcc_lo, v255 -// W64: v_cmp_class_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc_lo, v127, v255 -// W32: v_cmp_class_f16_e64 vcc_lo, v127, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x7f,0xff,0x03,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, v128.h, v2.h +// W64: v_cmp_class_f16_e64 vcc, v128.h, v2.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, v128.l, v2.l +// W64: v_cmp_class_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x80,0x05,0x02,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_class_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, vcc_hi, v255.h +// W64: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, vcc_hi, v255.l +// W64: v_cmp_class_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +v_cmp_class_f16 vcc, vcc_lo, v255.h +// W64: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc, vcc_lo, v255.l +// W64: v_cmp_class_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, v127.h, v255.h +// W32: v_cmp_class_f16_e64 vcc_lo, v127.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00] // W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +v_cmp_class_f16 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc_lo, v128, v2 -// W32: v_cmp_class_f16_e64 vcc_lo, v128, v2 ; encoding: [0x6a,0x00,0x7d,0xd4,0x80,0x05,0x02,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +v_cmp_class_f16 vcc_lo, v127.l, v255.l +// W32: v_cmp_class_f16_e64 vcc_lo, v127.l, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x7f,0xff,0x03,0x00] // W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_class_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +v_cmp_class_f16 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc_lo, vcc_hi, v255 -// W32: v_cmp_class_f16_e64 vcc_lo, vcc_hi, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction -v_cmp_class_f16 vcc_lo, vcc_lo, v255 -// W32: v_cmp_class_f16_e64 vcc_lo, vcc_lo, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_class_f16 vcc_lo, v128.h, v2.h +// W32: v_cmp_class_f16_e64 vcc_lo, v128.h, v2.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, v128.l, v2.l +// W32: v_cmp_class_f16_e64 vcc_lo, v128.l, v2.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x80,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_class_f16_e64_dpp vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, vcc_hi, v255.h +// W32: v_cmp_class_f16_e64 vcc_lo, vcc_hi, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, vcc_hi, v255.l +// W32: v_cmp_class_f16_e64 vcc_lo, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, vcc_lo, v255.h +// W32: v_cmp_class_f16_e64 vcc_lo, vcc_lo, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction + +v_cmp_class_f16 vcc_lo, vcc_lo, v255.l +// W32: v_cmp_class_f16_e64 vcc_lo, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction v_cmp_eq_f16 vcc, v1, v255 // W64: v_cmp_eq_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt index 4e2527cc2fa2f..e0a02daa7f13e 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt @@ -5,59 +5,100 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] 0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s104, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] 0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01 -# W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] -# W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +# W32-REAL16: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] 0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13 -# W32: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] -# W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W32-REAL16: v_cmp_class_f16_e64_dpp ttmp14, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] 0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30 -# GFX11: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W32-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W32-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W64-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W64-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] + +0x7a,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13 +# W32-REAL16: v_cmp_class_f16_e64_dpp ttmp14, v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] + +0x7c,0x11,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30 +# W32-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W32-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W64-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W64-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] 0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff # W32: v_cmp_class_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt index f399fe7f0aef4..ea796f38fd5a2 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt @@ -5,23 +5,46 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp s104, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp ttmp14, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00 -# GFX11: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W32-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +0x7a,0x08,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 +# W32-REAL16: v_cmp_class_f16_e64_dpp ttmp14, v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x08,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x08,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +0x7c,0x11,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00 +# W32-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] 0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 # W32: v_cmp_class_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt index 350087218d366..47215a9e2b115 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt @@ -5,24 +5,34 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00 -# W32: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] 0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00 -# W32: v_cmp_class_f16_e64 s10, v1, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], v1, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, v1.l, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, v1, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], v1.l, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], v1, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00] 0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00 -# W32: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, v255.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], v255.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] 0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00 -# W32: v_cmp_class_f16_e64 s10, s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, s1, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], s1, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] 0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00 -# W32: v_cmp_class_f16_e64 s10, s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, s105, v255.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], s105, v255.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] 0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00 # W32: v_cmp_class_f16_e64 s10, vcc_lo, s2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00] @@ -67,6 +77,18 @@ 0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00 # GFX11: v_cmp_class_f16_e64 null, -|0xfe0b|, vcc_hi ; encoding: [0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00] +0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00 +# W32-REAL16: v_cmp_class_f16_e64 s10, v255.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], v255.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] + +0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00 +# W32-REAL16: v_cmp_class_f16_e64 s10, s105, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], s105, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] + 0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00 # W32: v_cmp_class_f32_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00] # W64: v_cmp_class_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt index 7f2de110be37d..bd114ebed172f 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt @@ -5,64 +5,124 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0x01,0x05,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] 0x7f,0x05,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] 0x01,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] 0x69,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] 0x6a,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] 0x6b,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] 0x7b,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] 0x7d,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] 0x7e,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] 0x7f,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] 0x7c,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] 0xc1,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] 0xf0,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] 0xfd,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] 0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00 -# W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] -# W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +# W64-REAL16: v_cmp_class_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] + +0x81,0x05,0xfa,0x7c +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0xfa,0x7c] + +0xff,0x05,0xfa,0x7c +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0xfa,0x7c] + +0xf0,0xfe,0xfa,0x7c +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, 0.5, v127 ; encoding: [0xf0,0xfe,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, 0.5, v127 ; encoding: [0xf0,0xfe,0xfa,0x7c] + +0xfd,0x04,0xfb,0x7c +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0xfb,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0xfb,0x7c] + +0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00 +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] +# W64-REAL16: v_cmp_class_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] 0x01,0x05,0xfc,0x7c # W32: v_cmp_class_f32_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfc,0x7c] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt index da691eebd06c4..924edb35727fa 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt @@ -5,60 +5,106 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01 -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] -# W64: v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13 -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] -# W64: v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] 0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30 -# W32: v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] -# W64: v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] +# W32-REAL16: v_cmp_class_f16 vcc_lo, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] +# W64-REAL16: v_cmp_class_f16 vcc, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] +# W64-FAKE16: v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] + +0xfa,0xfe,0xfa,0x7c,0x7f,0x5f,0x01,0x01 +# W32-REAL16: v_cmp_class_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_class_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v127, v127 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_class_f16 vcc, v127, v127 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x5f,0x01,0x01] + +0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13 +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13] +# W64-REAL16: v_cmp_class_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_class_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13] + +0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30 +# W32-REAL16: v_cmp_class_f16 vcc_lo, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30] +# W64-REAL16: v_cmp_class_f16 vcc, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30] +# W64-FAKE16: v_cmp_class_f16 vcc, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30] 0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff # W32: v_cmp_class_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt index 998f8ea6618ca..64f4cfb9e7a73 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt @@ -5,12 +5,34 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] 0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00 -# W32: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] -# W64: v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +# W64-REAL16: v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] + +0xe9,0xfe,0xfa,0x7c,0x7f,0x77,0x39,0x05 +# W32-REAL16: v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16 vcc, v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x77,0x39,0x05] + +0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05 +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] + +0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00 +# W32-REAL16: v_cmp_class_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_class_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16 vcc, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] 0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05 # W32: v_cmp_class_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt index aa3d350134424..18dda0b132c75 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt @@ -5,20 +5,28 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00 -# W32: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] 0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00 -# W32: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, v255.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], v255.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] 0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00 -# W32: v_cmp_class_f16_e64 s10, s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, s1, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], s1, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00] 0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00 -# W32: v_cmp_class_f16_e64 s10, s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] -# W64: v_cmp_class_f16_e64 s[10:11], s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W32-REAL16: v_cmp_class_f16_e64 s10, s105, v255.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], s105, v255.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] 0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00 # W32: v_cmp_class_f16_e64 s10, vcc_lo, s2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00] @@ -63,6 +71,19 @@ 0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00 # GFX12: v_cmp_class_f16_e64 null, -|0xfe0b|, vcc_hi ; encoding: [0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00] +0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00 +# W32-REAL16: v_cmp_class_f16_e64 s10, v255.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], v255.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00] + +0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00 +# W32-REAL16: v_cmp_class_f16_e64 s10, s105, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W32-FAKE16: v_cmp_class_f16_e64 s10, s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W64-REAL16: v_cmp_class_f16_e64 s[10:11], s105, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00] +# W64-FAKE16: v_cmp_class_f16_e64 s[10:11], s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00] + + 0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00 # W32: v_cmp_class_f32_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00] # W64: v_cmp_class_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt index 487a71d59e273..667d67625ee4a 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt @@ -5,63 +5,106 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] 0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff -# W32: v_cmp_class_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] -# W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W32-REAL16: v_cmp_class_f16_e64_dpp s104, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] 0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01 -# W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] -# W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +# W32-REAL16: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] 0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13 -# W32: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] -# W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W32-REAL16: v_cmp_class_f16_e64_dpp ttmp14, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] 0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30 -# GFX12: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W32-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W32-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W64-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W64-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] + +0x7a,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13 +# W32-REAL16: v_cmp_class_f16_e64_dpp ttmp14, v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x08,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] + +0x7c,0x11,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30 +# W32-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W32-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W64-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] +# W64-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30] 0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff # W32: v_cmp_class_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt index 3fc6cbf4e3cd4..551f47dec0ac5 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt @@ -5,31 +5,58 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp s10, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] 0x0a,0x00,0x7d,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp s10, v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp s10, v1.l, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s10, v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[10:11], v1.l, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[10:11], v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] 0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp s104, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16_e64_dpp ttmp14, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00 -# GFX12: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W32-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +0x7a,0x08,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 +# W32-REAL16: v_cmp_class_f16_e64_dpp ttmp14, v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x08,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x08,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +0x7c,0x11,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00 +# W32-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_class_f16_e64_dpp null, -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x11,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] 0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 # W32: v_cmp_class_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt index 3048b8553c7ec..d4c55dc85c43c 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt @@ -5,64 +5,118 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0x01,0x05,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] 0x7f,0x05,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7c] 0x01,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0xfa,0x7c] 0x69,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0xfa,0x7c] 0x6a,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7c] 0x6b,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7c] 0x7b,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7c] 0x7d,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7c] 0x7e,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7c] 0x7f,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7c] 0x7c,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0xfa,0x7c] 0xc1,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7c] 0xf0,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7c] 0xfd,0x04,0xfa,0x7c -# W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] -# W64: v_cmp_class_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7c] 0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00 -# W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] -# W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +# W64-REAL16: v_cmp_class_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00] + +0x81,0x05,0xfa,0x7c +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0xfa,0x7c] + +0xff,0x05,0xfa,0x7c +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0xfa,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0xfa,0x7c] + +0xfd,0x04,0xfb,0x7c +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c] +# W64-REAL16: v_cmp_class_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0xfb,0x7c] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0xfb,0x7c] + +0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00 +# W32-REAL16: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] +# W64-REAL16: v_cmp_class_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16_e32 vcc, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0xfb,0x7c,0x0b,0xfe,0x00,0x00] 0x01,0x05,0xfc,0x7c # W32: v_cmp_class_f32_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfc,0x7c] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt index 213a79fdc8ed4..879e1c02c8cab 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt @@ -5,60 +5,100 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] -# W64: v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff] 0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01 -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] -# W64: v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13 -# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] -# W64: v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13] 0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30 -# W32: v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] -# W64: v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] +# W32-REAL16: v_cmp_class_f16 vcc_lo, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] +# W64-REAL16: v_cmp_class_f16 vcc, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] +# W64-FAKE16: v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30] + +0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13 +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13] +# W64-REAL16: v_cmp_class_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_class_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7c,0x81,0x60,0x01,0x13] + +0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30 +# W32-REAL16: v_cmp_class_f16 vcc_lo, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30] +# W64-REAL16: v_cmp_class_f16 vcc, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30] +# W64-FAKE16: v_cmp_class_f16 vcc, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7c,0xff,0x6f,0x3d,0x30] 0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff # W32: v_cmp_class_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt index 3ff28315626e9..bc0792c389bda 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt @@ -5,12 +5,29 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05 -# W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] -# W64: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] 0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00 -# W32: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] -# W64: v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +# W32-REAL16: v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +# W64-REAL16: v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00] + +0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05 +# W32-REAL16: v_cmp_class_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +# W64-REAL16: v_cmp_class_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_class_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7c,0x81,0x77,0x39,0x05] + +0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00 +# W32-REAL16: v_cmp_class_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_class_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_class_f16 vcc_lo, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_class_f16 vcc, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00] + 0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05 # W32: v_cmp_class_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05]