diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 0ebe845e473fd..edb85d212a4d4 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -190,7 +190,8 @@ class RegReloadCache {
   // Does basic block MBB contains reload of Reg from FI?
   bool hasReload(Register Reg, int FI, const MachineBasicBlock *MBB) {
     RegSlotPair RSP(Reg, FI);
-    return Reloads.count(MBB) && Reloads[MBB].count(RSP);
+    auto It = Reloads.find(MBB);
+    return It != Reloads.end() && It->second.count(RSP);
   }
 };
 
@@ -242,9 +243,10 @@ class FrameIndexesCache {
       It.second.Index = 0;
 
     ReservedSlots.clear();
-    if (EHPad && GlobalIndices.count(EHPad))
-      for (auto &RSP : GlobalIndices[EHPad])
-        ReservedSlots.insert(RSP.second);
+    if (EHPad)
+      if (auto It = GlobalIndices.find(EHPad); It != GlobalIndices.end())
+        for (auto &RSP : It->second)
+          ReservedSlots.insert(RSP.second);
   }
 
   // Get frame index to spill the register.