From f8a386cf3322a161686282865e2a1b9cf8e5a429 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 22 Jan 2025 18:02:40 -0800 Subject: [PATCH 1/2] [RISCV] Add RVVConstraint=VS2Constraint to SiFive custom matrix multiply instructions. The instructions don't allow the vs1 encoded register to overlap vd. Confusingly these instructions order their operands vd, vs1, vs2 while every other vector instruction is vd, vs2, vs1. VS2Constraint really means check the first operand after vd which is vs1 in this case. --- llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 6 ++-- llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s | 6 ++++ llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s | 34 +++++++++++++++++++++ 3 files changed, 43 insertions(+), 3 deletions(-) create mode 100644 llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s create mode 100644 llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 20adda91f6bde..117789c0fb278 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -202,7 +202,7 @@ let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0, } let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod", - DestEEW = EEWSEWx4 in { + DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in { def VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">; def VQMACC_2x8x2 : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">; def VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">; @@ -210,7 +210,7 @@ let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod", } let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq", - DestEEW = EEWSEWx4 in { + DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in { def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">; def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">; def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">; @@ -218,7 +218,7 @@ let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq", } let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq", - DestEEW = EEWSEWx2 in { + DestEEW = EEWSEWx2, RVVConstraint=VS2Constraint in { def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">; } diff --git a/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s b/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s new file mode 100644 index 0000000000000..357afb03af182 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+xsfvfwmaccqqq %s 2>&1 \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR + +sf.vfwmacc.4x4x4 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vfwmacc.4x4x4 v8, v8, v20{{$}} diff --git a/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s b/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s new file mode 100644 index 0000000000000..aaf35322eede6 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s @@ -0,0 +1,34 @@ +# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +sf.vqmaccu.2x8x2 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccu.2x8x2 v8, v8, v20 + +sf.vqmacc.2x8x2 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmacc.2x8x2 v8, v8, v20 + +sf.vqmaccus.2x8x2 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccus.2x8x2 v8, v8, v20 + +sf.vqmaccsu.2x8x2 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccsu.2x8x2 v8, v8, v20 + +sf.vqmaccu.4x8x4 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccu.4x8x4 v8, v8, v20 + +sf.vqmacc.4x8x4 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmacc.4x8x4 v8, v8, v20 + +sf.vqmaccus.4x8x4 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccus.4x8x4 v8, v8, v20 + +sf.vqmaccsu.4x8x4 v8, v8, v20 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccsu.4x8x4 v8, v8, v20 From f55f90c2f1861752fa23bf3e66b1555cfb489f46 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 22 Jan 2025 19:54:07 -0800 Subject: [PATCH 2/2] fixup! Use WidenV for vfwmacc.4x4x4 and vqmacc*.4x8x4. --- llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 4 ++-- llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s | 4 ++++ llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s | 16 ++++++++++++++++ 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 117789c0fb278..d5105a9edb029 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -210,7 +210,7 @@ let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod", } let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq", - DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in { + DestEEW = EEWSEWx4, RVVConstraint=WidenV in { def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">; def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">; def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">; @@ -218,7 +218,7 @@ let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq", } let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq", - DestEEW = EEWSEWx2, RVVConstraint=VS2Constraint in { + DestEEW = EEWSEWx2, RVVConstraint=WidenV in { def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">; } diff --git a/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s b/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s index 357afb03af182..452778613adf6 100644 --- a/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s +++ b/llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s @@ -4,3 +4,7 @@ sf.vfwmacc.4x4x4 v8, v8, v20 # CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} # CHECK-ERROR-LABEL: sf.vfwmacc.4x4x4 v8, v8, v20{{$}} + +sf.vfwmacc.4x4x4 v8, v4, v8 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vfwmacc.4x4x4 v8, v4, v8{{$}} diff --git a/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s b/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s index aaf35322eede6..a7cbfbcb1f365 100644 --- a/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s +++ b/llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s @@ -32,3 +32,19 @@ sf.vqmaccus.4x8x4 v8, v8, v20 sf.vqmaccsu.4x8x4 v8, v8, v20 # CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} # CHECK-ERROR-LABEL: sf.vqmaccsu.4x8x4 v8, v8, v20 + +sf.vqmaccu.4x8x4 v8, v4, v8 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccu.4x8x4 v8, v4, v8 + +sf.vqmacc.4x8x4 v8, v4, v8 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmacc.4x8x4 v8, v4, v8 + +sf.vqmaccus.4x8x4 v8, v4, v8 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccus.4x8x4 v8, v4, v8 + +sf.vqmaccsu.4x8x4 v8, v4, v8 +# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}} +# CHECK-ERROR-LABEL: sf.vqmaccsu.4x8x4 v8, v4, v8