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[RISCV] Add RVVConstraint to SiFive custom matrix multiply instructions. #124055

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Merged
topperc merged 2 commits into from
Jan 23, 2025
Merged

[RISCV] Add RVVConstraint to SiFive custom matrix multiply instructions. #124055

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f8a386c
[RISCV] Add RVVConstraint=VS2Constraint to SiFive custom matrix multi…
topperc Jan 23, 2025
f55f90c
fixup! Use WidenV for vfwmacc.4x4x4 and vqmacc*.4x8x4.
topperc Jan 23, 2025
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6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
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Original file line number Diff line number Diff line change
Expand Up @@ -202,23 +202,23 @@ let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0,
}

let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod",
DestEEW = EEWSEWx4 in {
DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in {
def VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">;
def VQMACC_2x8x2 : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">;
def VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">;
def VQMACCSU_2x8x2 : CustomSiFiveVMACC<0b101111, OPMVV, "sf.vqmaccsu.2x8x2">;
}

let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq",
DestEEW = EEWSEWx4 in {
DestEEW = EEWSEWx4, RVVConstraint=WidenV in {
def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">;
def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">;
def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">;
def VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">;
}

let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq",
DestEEW = EEWSEWx2 in {
DestEEW = EEWSEWx2, RVVConstraint=WidenV in {
def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;
}

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10 changes: 10 additions & 0 deletions llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+xsfvfwmaccqqq %s 2>&1 \
# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR

sf.vfwmacc.4x4x4 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vfwmacc.4x4x4 v8, v8, v20{{$}}

sf.vfwmacc.4x4x4 v8, v4, v8
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vfwmacc.4x4x4 v8, v4, v8{{$}}
50 changes: 50 additions & 0 deletions llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,50 @@
# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR

sf.vqmaccu.2x8x2 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccu.2x8x2 v8, v8, v20

sf.vqmacc.2x8x2 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmacc.2x8x2 v8, v8, v20

sf.vqmaccus.2x8x2 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccus.2x8x2 v8, v8, v20

sf.vqmaccsu.2x8x2 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccsu.2x8x2 v8, v8, v20

sf.vqmaccu.4x8x4 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccu.4x8x4 v8, v8, v20

sf.vqmacc.4x8x4 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmacc.4x8x4 v8, v8, v20

sf.vqmaccus.4x8x4 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccus.4x8x4 v8, v8, v20

sf.vqmaccsu.4x8x4 v8, v8, v20
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccsu.4x8x4 v8, v8, v20

sf.vqmaccu.4x8x4 v8, v4, v8
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccu.4x8x4 v8, v4, v8

sf.vqmacc.4x8x4 v8, v4, v8
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmacc.4x8x4 v8, v4, v8

sf.vqmaccus.4x8x4 v8, v4, v8
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccus.4x8x4 v8, v4, v8

sf.vqmaccsu.4x8x4 v8, v4, v8
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group{{$}}
# CHECK-ERROR-LABEL: sf.vqmaccsu.4x8x4 v8, v4, v8
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