From 95b887cdedb8471590e3227907e3d6e39fb7cd44 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Thu, 23 Jan 2025 13:10:29 -0800 Subject: [PATCH] [RISCV][VLOPT] support fp sign injection instructions --- llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 7 ++ llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 120 +++++++++++++++++++ 2 files changed, 127 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index dcd02cdb0728b..976c65e51c205 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -1022,6 +1022,13 @@ static bool isSupportedInstr(const MachineInstr &MI) { case RISCV::VFMIN_VV: case RISCV::VFMAX_VF: case RISCV::VFMAX_VV: + // Vector Floating-Point Sign-Injection Instructions + case RISCV::VFSGNJ_VF: + case RISCV::VFSGNJ_VV: + case RISCV::VFSGNJN_VV: + case RISCV::VFSGNJN_VF: + case RISCV::VFSGNJX_VF: + case RISCV::VFSGNJX_VV: // Vector Floating-Point Compare Instructions case RISCV::VMFEQ_VF: case RISCV::VMFEQ_VV: diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll index 7b9c042cc0944..5ca2be8da6f3c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll @@ -3911,3 +3911,123 @@ define @vfmin_vx( %a, float %b, iXLen % %2 = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( poison, %1, %a, iXLen 7, iXLen %vl) ret %2 } + +define @vfsgnj_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vfsgnj_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vfsgnj.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vfadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vfsgnj_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vfsgnj.vv v8, v8, v10 +; VLOPT-NEXT: vfadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vfsgnj.nxv4f32.nxv4f32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( poison, %1, %b, iXLen 7, iXLen %vl) + ret %2 +} + +define @vfsgnj_vf( %a, float %b, iXLen %vl) { +; NOVLOPT-LABEL: vfsgnj_vf: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vfsgnj.vf v10, v8, fa0 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vfadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vfsgnj_vf: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vfsgnj.vf v10, v8, fa0 +; VLOPT-NEXT: vfadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vfsgnj.nxv4f32.nxv4f32( poison, %a, float %b, iXLen -1) + %2 = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( poison, %1, %a, iXLen 7, iXLen %vl) + ret %2 +} + +define @vfsgnjn_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vfsgnjn_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vfsgnjn.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vfadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vfsgnjn_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vfsgnjn.vv v8, v8, v10 +; VLOPT-NEXT: vfadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( poison, %1, %b, iXLen 7, iXLen %vl) + ret %2 +} + +define @vfsgnjn_vf( %a, float %b, iXLen %vl) { +; NOVLOPT-LABEL: vfsgnjn_vf: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vfsgnjn.vf v10, v8, fa0 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vfadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vfsgnjn_vf: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vfsgnjn.vf v10, v8, fa0 +; VLOPT-NEXT: vfadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32( poison, %a, float %b, iXLen -1) + %2 = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( poison, %1, %a, iXLen 7, iXLen %vl) + ret %2 +} + +define @vfsgnjx_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vfsgnjx_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vfsgnjx.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vfadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vfsgnjx_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vfsgnjx.vv v8, v8, v10 +; VLOPT-NEXT: vfadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( poison, %1, %b, iXLen 7, iXLen %vl) + ret %2 +} + +define @vfsgnjx_vf( %a, float %b, iXLen %vl) { +; NOVLOPT-LABEL: vfsgnjx_vf: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vfsgnjx.vf v10, v8, fa0 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vfadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vfsgnjx_vf: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vfsgnjx.vf v10, v8, fa0 +; VLOPT-NEXT: vfadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32( poison, %a, float %b, iXLen -1) + %2 = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( poison, %1, %a, iXLen 7, iXLen %vl) + ret %2 +}