From f1c75e4b1bec64ddfc4100fc8fabfd2e1d64b560 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 29 Jan 2025 13:43:37 +0700
Subject: [PATCH] SystemZ: Handle copies between gr64 and fp64

I'm guessing based on tablegen definitions. I also don't
really understand how this could have been missing.

This defends against regressions in a future peephole-opt
patch.
---
 llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp  |  6 +++
 .../SystemZ/copy-phys-reg-fp64-to-gr64.mir    | 48 +++++++++++++++++++
 .../SystemZ/copy-phys-reg-gr64-to-fp64.mir    | 47 ++++++++++++++++++
 3 files changed, 101 insertions(+)
 create mode 100644 llvm/test/CodeGen/SystemZ/copy-phys-reg-fp64-to-gr64.mir
 create mode 100644 llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir

diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index a6fb5ab0ee9e1..8a32d998fce2c 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -983,6 +983,12 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     Opcode = SystemZ::VLR;
   else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
     Opcode = SystemZ::CPYA;
+  else if (SystemZ::GR64BitRegClass.contains(DestReg) &&
+           SystemZ::FP64BitRegClass.contains(SrcReg))
+    Opcode = SystemZ::LGDR;
+  else if (SystemZ::FP64BitRegClass.contains(DestReg) &&
+           SystemZ::GR64BitRegClass.contains(SrcReg))
+    Opcode = SystemZ::LDGR;
   else
     llvm_unreachable("Impossible reg-to-reg copy");
 
diff --git a/llvm/test/CodeGen/SystemZ/copy-phys-reg-fp64-to-gr64.mir b/llvm/test/CodeGen/SystemZ/copy-phys-reg-fp64-to-gr64.mir
new file mode 100644
index 0000000000000..6fd09d25216e7
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/copy-phys-reg-fp64-to-gr64.mir
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s
+
+---
+name:            copy_fp64_to_gr64__r1d_to_f3d
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r1d
+    ; CHECK-LABEL: name: copy_fp64_to_gr64__r1d_to_f3d
+    ; CHECK: liveins: $r1d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $f3d = LDGR $r1d
+    ; CHECK-NEXT: Return implicit $f3d
+    $f3d = COPY $r1d
+    Return implicit $f3d
+...
+
+---
+name:            copy_fp64_to_gr64__r1d_to_f3d_undef
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r1d
+    ; CHECK-LABEL: name: copy_fp64_to_gr64__r1d_to_f3d_undef
+    ; CHECK: liveins: $r1d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $f3d = KILL undef $r1d
+    ; CHECK-NEXT: Return implicit $f3d
+    $f3d = COPY undef $r1d
+    Return implicit $f3d
+...
+
+---
+name:            copy_fp64_to_gr64__r1d_to_f3d_killed
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r1d
+    ; CHECK-LABEL: name: copy_fp64_to_gr64__r1d_to_f3d_killed
+    ; CHECK: liveins: $r1d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $f3d = LDGR killed $r1d
+    ; CHECK-NEXT: Return implicit $f3d
+    $f3d = COPY killed $r1d
+    Return implicit $f3d
+...
+
diff --git a/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir b/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir
new file mode 100644
index 0000000000000..07ef93415bb79
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s
+---
+name:            copy_fp64_to_gr64__f3d_to_r1d
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f3d
+    ; CHECK-LABEL: name: copy_fp64_to_gr64__f3d_to_r1d
+    ; CHECK: liveins: $f3d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r1d = LGDR $f3d
+    ; CHECK-NEXT: Return implicit $r1d
+    $r1d = COPY $f3d
+    Return implicit $r1d
+...
+
+---
+name:            copy_fp64_to_gr64__f3d_to_r1d_undef
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f3d
+    ; CHECK-LABEL: name: copy_fp64_to_gr64__f3d_to_r1d_undef
+    ; CHECK: liveins: $f3d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r1d = KILL undef $f3d
+    ; CHECK-NEXT: Return implicit $r1d
+    $r1d = COPY undef $f3d
+    Return implicit $r1d
+...
+
+---
+name:            copy_fp64_to_gr64__f3d_to_r1d_killed
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f3d
+    ; CHECK-LABEL: name: copy_fp64_to_gr64__f3d_to_r1d_killed
+    ; CHECK: liveins: $f3d
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r1d = LGDR killed $f3d
+    ; CHECK-NEXT: Return implicit $r1d
+    $r1d = COPY killed $f3d
+    Return implicit $r1d
+...
+