From 31274e05889e5dfa71c4c55bfdbc95fa2a1437fb Mon Sep 17 00:00:00 2001 From: zhijian Date: Wed, 5 Feb 2025 17:04:32 +0000 Subject: [PATCH 1/8] introduce a new ISDNODE POISON --- llvm/include/llvm/CodeGen/ISDOpcodes.h | 3 +++ llvm/include/llvm/CodeGen/SelectionDAG.h | 3 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 16 ++++++++++++++-- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 ++- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 17 +++++++++++++++++ .../SelectionDAG/LegalizeIntegerTypes.cpp | 2 ++ .../SelectionDAG/LegalizeVectorTypes.cpp | 3 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 9 +++++++++ .../SelectionDAG/SelectionDAGBuilder.cpp | 2 +- .../CodeGen/SelectionDAG/SelectionDAGDumper.cpp | 1 + .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 1 + 11 files changed, 56 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index 59f31f8443947..ad8a95a353b56 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -217,6 +217,9 @@ enum NodeType { /// UNDEF - An undefined node. UNDEF, + /// POISON - A poison node. + POISON, + /// FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or /// is evaluated to UNDEF), or returns VAL otherwise. Note that each /// read of UNDEF can yield different value, but FREEZE(UNDEF) cannot. diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index 15a2370e5d8b8..956e5daa52131 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1130,6 +1130,9 @@ class SelectionDAG { return getNode(ISD::UNDEF, SDLoc(), VT); } + /// Return an POISON node. POISON does not have a useful SDLoc. + SDValue getPoison(EVT VT) { return getNode(ISD::POISON, SDLoc(), VT); } + /// Return a node that represents the runtime scaling 'MulImm * RuntimeVL'. SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold = true); diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 2283f99202e2f..3d49aabfcb079 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -692,8 +692,20 @@ END_TWO_BYTE_PACK() /// \ISD namespace). bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; } - /// Return true if the type of the node type undefined. - bool isUndef() const { return NodeType == ISD::UNDEF; } + /// Returns true if the node type is UNDEF or, when DoNotIncludeExplicitPoison + /// is false, POISON. + /// - When DoNotIncludeExplicitPoison is true, returns true only for UNDEF. + /// - When DoNotIncludeExplicitPoison is false, returns true for both UNDEF + /// and POISON. + /// @param DoNotIncludeExplicitPoison Determines whether to check only for + /// UNDEF. + bool isUndef(bool DoNotIncludeExplicitPoison = false) const { + return NodeType == ISD::UNDEF || + (!DoNotIncludeExplicitPoison && NodeType == ISD::POISON); + } + + /// Return true if the type of the node type poison. + bool isPoison() const { return NodeType == ISD::POISON; } /// Test if this node is a memory intrinsic (with valid pointer information). bool isMemIntrinsic() const { return SDNodeBits.IsMemIntrinsic; } diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index a54857e1037e2..3c92d9d8c7b7d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -16266,7 +16266,8 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { // Finally, recreate the node, it's operands were updated to use // frozen operands, so we just need to use it's "original" operands. SmallVector Ops(N0->ops()); - // Special-handle ISD::UNDEF, each single one of them can be it's own thing. + // Special-handle ISD::UNDEF, ISD::POISON, each single one of them can be it's + // own thing. for (SDValue &Op : Ops) { if (Op.isUndef()) Op = DAG.getFreeze(Op); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 1cacab9528caa..adfee457a7c9e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -977,6 +977,22 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { TargetLowering::LegalizeAction Action = TargetLowering::Legal; bool SimpleFinishLegalizing = true; switch (Node->getOpcode()) { + // FIXME: If the node represents a poison value, replace it with an undef + // value. + // A poison value results from an erroneous operation but does not cause + // immediate undefined behavior, allowing speculative execution. + // Since most operations propagate poison, it is valid to replace poison + // with an undef value, which can take any legal value of the same type. + // This ensures that downstream computations do not rely on poison semantics. + // Poison is more restrictive than undef. Since we replace poison with undef + // here, the poison information will be lost after the code is executed. In + // the futher, If we need to retain the poison information after the code is + // executed, we will need to modify the code accordingly. + case ISD::POISON: { + SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0)); + ReplaceNode(Node, UndefNode.getNode()); + break; + } case ISD::INTRINSIC_W_CHAIN: case ISD::INTRINSIC_WO_CHAIN: case ISD::INTRINSIC_VOID: @@ -3139,6 +3155,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { for (unsigned i = 0; i < Node->getNumValues(); i++) Results.push_back(Node->getOperand(i)); break; + case ISD::POISON: case ISD::UNDEF: { EVT VT = Node->getValueType(0); if (VT.isInteger()) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 204b323d7084a..f944104a0e9d6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -118,6 +118,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break; case ISD::VP_TRUNCATE: case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; + case ISD::POISON: case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break; @@ -2932,6 +2933,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break; case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; + case ISD::POISON: case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break; case ISD::SETCC: ExpandIntRes_SETCC(N, Lo, Hi); break; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 9d42ec2fdf859..f934d8b37561e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -71,6 +71,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; + case ISD::POISON: case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; case ISD::IS_FPCLASS: R = ScalarizeVecRes_IS_FPCLASS(N); break; @@ -1137,6 +1138,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { case ISD::VP_MERGE: case ISD::VP_SELECT: SplitRes_Select(N, Lo, Hi); break; case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; + case ISD::POISON: case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; @@ -4592,6 +4594,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; case ISD::VP_SETCC: case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; + case ISD::POISON: case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; case ISD::VECTOR_SHUFFLE: Res = WidenVecRes_VECTOR_SHUFFLE(cast(N)); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index d1f92c9ef00e9..c7662da69b9d6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5406,6 +5406,9 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, case ISD::CopyFromReg: return true; + case ISD::POISON: + return false; + case ISD::UNDEF: return PoisonOnly; @@ -6259,6 +6262,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, if (N1.isUndef()) // sext(undef) = 0, because the top bits will all be the same. return getConstant(0, DL, VT); + break; case ISD::ZERO_EXTEND: assert(VT.isInteger() && N1.getValueType().isInteger() && @@ -9199,6 +9203,11 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, SDVTList VTs = Indexed ? getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); + + // Lower poison to undef. + if (Ptr.getNode()->isPoison()) + Ptr = getUNDEF(Ptr.getValueType()); + SDValue Ops[] = { Chain, Ptr, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::LOAD, VTs, Ops); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index e3c34382d6354..77d8faeed7bc1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -1817,7 +1817,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { return DAG.getConstantFP(*CFP, getCurSDLoc(), VT); if (isa(C) && !V->getType()->isAggregateType()) - return DAG.getUNDEF(VT); + return isa(C) ? DAG.getPoison(VT) : DAG.getUNDEF(VT); if (const ConstantExpr *CE = dyn_cast(C)) { visit(CE->getOpcode(), *CE); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index 64ecff8d71f98..f0cf315474268 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -185,6 +185,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::CopyToReg: return "CopyToReg"; case ISD::CopyFromReg: return "CopyFromReg"; case ISD::UNDEF: return "undef"; + case ISD::POISON: return "poison"; case ISD::VSCALE: return "vscale"; case ISD::MERGE_VALUES: return "merge_values"; case ISD::INLINEASM: return "inlineasm"; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 63ee2d78cfa1b..aeee0a1426f3d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3276,6 +3276,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, case ISD::WRITE_REGISTER: Select_WRITE_REGISTER(NodeToMatch); return; + case ISD::POISON: case ISD::UNDEF: Select_UNDEF(NodeToMatch); return; From ba656cd91f4305283ab00e924cc52d9f191865bc Mon Sep 17 00:00:00 2001 From: zhijian Date: Wed, 19 Feb 2025 15:17:02 +0000 Subject: [PATCH 2/8] address comment --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 3 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 11 ----------- 2 files changed, 14 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 3d49aabfcb079..ae38c2b6862b8 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -694,9 +694,6 @@ END_TWO_BYTE_PACK() /// Returns true if the node type is UNDEF or, when DoNotIncludeExplicitPoison /// is false, POISON. - /// - When DoNotIncludeExplicitPoison is true, returns true only for UNDEF. - /// - When DoNotIncludeExplicitPoison is false, returns true for both UNDEF - /// and POISON. /// @param DoNotIncludeExplicitPoison Determines whether to check only for /// UNDEF. bool isUndef(bool DoNotIncludeExplicitPoison = false) const { diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index adfee457a7c9e..ae02387139551 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -977,17 +977,6 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { TargetLowering::LegalizeAction Action = TargetLowering::Legal; bool SimpleFinishLegalizing = true; switch (Node->getOpcode()) { - // FIXME: If the node represents a poison value, replace it with an undef - // value. - // A poison value results from an erroneous operation but does not cause - // immediate undefined behavior, allowing speculative execution. - // Since most operations propagate poison, it is valid to replace poison - // with an undef value, which can take any legal value of the same type. - // This ensures that downstream computations do not rely on poison semantics. - // Poison is more restrictive than undef. Since we replace poison with undef - // here, the poison information will be lost after the code is executed. In - // the futher, If we need to retain the poison information after the code is - // executed, we will need to modify the code accordingly. case ISD::POISON: { SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0)); ReplaceNode(Node, UndefNode.getNode()); From 515a60d24822c20b4b43503d2ae752ad5b25a5ee Mon Sep 17 00:00:00 2001 From: zhijian Date: Tue, 4 Mar 2025 18:19:14 +0000 Subject: [PATCH 3/8] address comment --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 10 +++------- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 8 ++++++++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 4 ++++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 ---- llvm/test/CodeGen/X86/pr119158.ll | 7 ++++--- 5 files changed, 19 insertions(+), 14 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index ae38c2b6862b8..983297251e856 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -692,13 +692,9 @@ END_TWO_BYTE_PACK() /// \ISD namespace). bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; } - /// Returns true if the node type is UNDEF or, when DoNotIncludeExplicitPoison - /// is false, POISON. - /// @param DoNotIncludeExplicitPoison Determines whether to check only for - /// UNDEF. - bool isUndef(bool DoNotIncludeExplicitPoison = false) const { - return NodeType == ISD::UNDEF || - (!DoNotIncludeExplicitPoison && NodeType == ISD::POISON); + /// Returns true if the node type is UNDEF or POISON. + bool isUndef() const { + return NodeType == ISD::UNDEF || NodeType == ISD::POISON; } /// Return true if the type of the node type poison. diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index ae02387139551..ea7e57c88a788 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -977,6 +977,14 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { TargetLowering::LegalizeAction Action = TargetLowering::Legal; bool SimpleFinishLegalizing = true; switch (Node->getOpcode()) { + // TODO: Currently, POISON is being lowered to UNDEF here. However, there is + // an open concern that this transformation may not be ideal, as targets + // should ideally handle POISON directly. Changing this behavior would require + // adding support for POISON in TableGen, which is a large change. + // Additionally, many existing test cases rely on the current behavior (e.g., + // llvm/test/CodeGen/PowerPC/vec_shuffle.ll). A broader discussion and + // incremental changes might be needed to properly + // support POISON without breaking existing targets and tests. case ISD::POISON: { SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0)); ReplaceNode(Node, UndefNode.getNode()); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index f934d8b37561e..908e0b81dd777 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -7801,6 +7801,10 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl &LdChain, // Load information SDValue Chain = LD->getChain(); SDValue BasePtr = LD->getBasePtr(); + // Lower to undef if BasePtr is Poison + if (BasePtr.getNode()->isPoison()) + BasePtr = DAG.getUNDEF(BasePtr.getValueType()); + MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags(); AAMDNodes AAInfo = LD->getAAInfo(); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index c7662da69b9d6..5a03bc3eaed56 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -9204,10 +9204,6 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, SDVTList VTs = Indexed ? getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); - // Lower poison to undef. - if (Ptr.getNode()->isPoison()) - Ptr = getUNDEF(Ptr.getValueType()); - SDValue Ops[] = { Chain, Ptr, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::LOAD, VTs, Ops); diff --git a/llvm/test/CodeGen/X86/pr119158.ll b/llvm/test/CodeGen/X86/pr119158.ll index ca31df802c913..4a1da30ca6c25 100644 --- a/llvm/test/CodeGen/X86/pr119158.ll +++ b/llvm/test/CodeGen/X86/pr119158.ll @@ -5,9 +5,10 @@ define dso_local void @foo() #1 { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %newFuncRoot ; CHECK-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero -; CHECK-NEXT: vpbroadcastd {{.*#+}} ymm1 = [64,64,64,64,64,64,64,64] -; CHECK-NEXT: vpdpwssd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm1 -; CHECK-NEXT: vpsrld $7, %ymm1, %ymm0 +; CHECK-NEXT: vpbroadcastd {{.*#+}} ymm1 = [18,0,18,0,18,0,18,0,18,0,18,0,18,0,18,0] +; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0 +; CHECK-NEXT: vpsrld $7, %ymm0, %ymm0 ; CHECK-NEXT: vpackusdw %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] ; CHECK-NEXT: vmovdqu %ymm0, (%rax) From 6fa17c2aa3c5fef18a7d02814e8ef12bd70597cf Mon Sep 17 00:00:00 2001 From: zhijian Date: Thu, 20 Mar 2025 20:39:52 +0000 Subject: [PATCH 4/8] address comment --- .../SelectionDAG/LegalizeVectorTypes.cpp | 4 ---- llvm/test/CodeGen/X86/half.ll | 24 +++++++++---------- 2 files changed, 12 insertions(+), 16 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 908e0b81dd777..f934d8b37561e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -7801,10 +7801,6 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl &LdChain, // Load information SDValue Chain = LD->getChain(); SDValue BasePtr = LD->getBasePtr(); - // Lower to undef if BasePtr is Poison - if (BasePtr.getNode()->isPoison()) - BasePtr = DAG.getUNDEF(BasePtr.getValueType()); - MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags(); AAMDNodes AAInfo = LD->getAAInfo(); diff --git a/llvm/test/CodeGen/X86/half.ll b/llvm/test/CodeGen/X86/half.ll index 1b98886ba24e7..a64238170cef9 100644 --- a/llvm/test/CodeGen/X86/half.ll +++ b/llvm/test/CodeGen/X86/half.ll @@ -1991,8 +1991,8 @@ define void @pr63114() { ; CHECK-LIBCALL-LABEL: pr63114: ; CHECK-LIBCALL: # %bb.0: ; CHECK-LIBCALL-NEXT: movdqu (%rax), %xmm4 -; CHECK-LIBCALL-NEXT: pshuflw {{.*#+}} xmm0 = xmm4[0,1,3,3,4,5,6,7] -; CHECK-LIBCALL-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,1] +; CHECK-LIBCALL-NEXT: pshufhw {{.*#+}} xmm0 = xmm4[0,1,2,3,4,5,7,7] +; CHECK-LIBCALL-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; CHECK-LIBCALL-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,0,65535,65535,65535,65535] ; CHECK-LIBCALL-NEXT: pand %xmm1, %xmm0 ; CHECK-LIBCALL-NEXT: movq {{.*#+}} xmm2 = [0,0,0,15360,0,0,0,0] @@ -2001,8 +2001,8 @@ define void @pr63114() { ; CHECK-LIBCALL-NEXT: pand %xmm3, %xmm0 ; CHECK-LIBCALL-NEXT: movdqa {{.*#+}} xmm5 = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,60] ; CHECK-LIBCALL-NEXT: por %xmm5, %xmm0 -; CHECK-LIBCALL-NEXT: pshufhw {{.*#+}} xmm6 = xmm4[0,1,2,3,4,5,7,7] -; CHECK-LIBCALL-NEXT: pshufd {{.*#+}} xmm6 = xmm6[0,2,2,3] +; CHECK-LIBCALL-NEXT: pshuflw {{.*#+}} xmm6 = xmm4[0,1,3,3,4,5,6,7] +; CHECK-LIBCALL-NEXT: pshufd {{.*#+}} xmm6 = xmm6[0,0,2,1] ; CHECK-LIBCALL-NEXT: pand %xmm1, %xmm6 ; CHECK-LIBCALL-NEXT: por %xmm2, %xmm6 ; CHECK-LIBCALL-NEXT: pand %xmm3, %xmm6 @@ -2020,8 +2020,8 @@ define void @pr63114() { ; CHECK-LIBCALL-NEXT: por %xmm5, %xmm7 ; CHECK-LIBCALL-NEXT: movdqu %xmm7, 0 ; CHECK-LIBCALL-NEXT: movdqu %xmm4, 32 -; CHECK-LIBCALL-NEXT: movdqu %xmm6, 48 -; CHECK-LIBCALL-NEXT: movdqu %xmm0, 16 +; CHECK-LIBCALL-NEXT: movdqu %xmm6, 16 +; CHECK-LIBCALL-NEXT: movdqu %xmm0, 48 ; CHECK-LIBCALL-NEXT: retq ; ; BWON-F16C-LABEL: pr63114: @@ -2056,8 +2056,8 @@ define void @pr63114() { ; CHECK-I686-LABEL: pr63114: ; CHECK-I686: # %bb.0: ; CHECK-I686-NEXT: movdqu (%eax), %xmm6 -; CHECK-I686-NEXT: pshuflw {{.*#+}} xmm0 = xmm6[0,1,3,3,4,5,6,7] -; CHECK-I686-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,1] +; CHECK-I686-NEXT: pshufhw {{.*#+}} xmm0 = xmm6[0,1,2,3,4,5,7,7] +; CHECK-I686-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; CHECK-I686-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,0,65535,65535,65535,65535] ; CHECK-I686-NEXT: pand %xmm1, %xmm0 ; CHECK-I686-NEXT: movq {{.*#+}} xmm2 = [0,0,0,15360,0,0,0,0] @@ -2066,8 +2066,8 @@ define void @pr63114() { ; CHECK-I686-NEXT: pand %xmm3, %xmm0 ; CHECK-I686-NEXT: movdqa {{.*#+}} xmm4 = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,60] ; CHECK-I686-NEXT: por %xmm4, %xmm0 -; CHECK-I686-NEXT: pshufhw {{.*#+}} xmm5 = xmm6[0,1,2,3,4,5,7,7] -; CHECK-I686-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3] +; CHECK-I686-NEXT: pshuflw {{.*#+}} xmm5 = xmm6[0,1,3,3,4,5,6,7] +; CHECK-I686-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,0,2,1] ; CHECK-I686-NEXT: pand %xmm1, %xmm5 ; CHECK-I686-NEXT: por %xmm2, %xmm5 ; CHECK-I686-NEXT: pand %xmm3, %xmm5 @@ -2085,8 +2085,8 @@ define void @pr63114() { ; CHECK-I686-NEXT: por %xmm4, %xmm7 ; CHECK-I686-NEXT: movdqu %xmm7, 0 ; CHECK-I686-NEXT: movdqu %xmm6, 32 -; CHECK-I686-NEXT: movdqu %xmm5, 48 -; CHECK-I686-NEXT: movdqu %xmm0, 16 +; CHECK-I686-NEXT: movdqu %xmm5, 16 +; CHECK-I686-NEXT: movdqu %xmm0, 48 ; CHECK-I686-NEXT: retl %1 = load <24 x half>, ptr poison, align 2 %2 = shufflevector <24 x half> %1, <24 x half> poison, <8 x i32> From ea6dd3f1b3396871ca9f8a225f2637918f646317 Mon Sep 17 00:00:00 2001 From: zhijian Date: Fri, 21 Mar 2025 14:54:49 +0000 Subject: [PATCH 5/8] rebase the code and modify the file LegalizeFloatTypes.cpp for the test case CodeGen/AMDGPU/clamp.ll fail --- .../SelectionDAG/LegalizeFloatTypes.cpp | 1 + .../AArch64/vector-insert-dag-combines.ll | 38 +++++++++---------- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 01751dfe9eb62..5ed83060e150e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -2845,6 +2845,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) { case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break; + case ISD::POISON: case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break; case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break; case ISD::VECREDUCE_FADD: diff --git a/llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll b/llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll index 0e05a63ef86de..5207d5cbf21a2 100644 --- a/llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll +++ b/llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll @@ -12,7 +12,7 @@ target triple = "aarch64-unknown-linux-gnu" ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0 ; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0> -; CHECK: t6: v16i8 = insert_subvector undef:v16i8, t4, Constant:i64<0> +; CHECK: t6: v16i8 = insert_subvector poison:v16i8, t4, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t6 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1 @@ -20,7 +20,7 @@ target triple = "aarch64-unknown-linux-gnu" ; CHECK: SelectionDAG has 9 nodes: ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0 -; CHECK: t10: v16i8 = insert_subvector undef:v16i8, t2, Constant:i64<0> +; CHECK: t10: v16i8 = insert_subvector poison:v16i8, t2, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t10 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1 @@ -35,7 +35,7 @@ define <16 x i8> @insert_small_fixed_into_big_fixed(<8 x i8> %a) #0 { ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0 ; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0> -; CHECK: t6: nxv16i8 = insert_subvector undef:nxv16i8, t4, Constant:i64<0> +; CHECK: t6: nxv16i8 = insert_subvector poison:nxv16i8, t4, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t6 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1 @@ -43,7 +43,7 @@ define <16 x i8> @insert_small_fixed_into_big_fixed(<8 x i8> %a) #0 { ; CHECK: SelectionDAG has 9 nodes: ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0 -; CHECK: t10: nxv16i8 = insert_subvector undef:nxv16i8, t2, Constant:i64<0> +; CHECK: t10: nxv16i8 = insert_subvector poison:nxv16i8, t2, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t10 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1 @@ -59,7 +59,7 @@ define @insert_small_fixed_into_big_scalable(<8 x i8> %a) #0 ; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0 ; CHECK: t3: nxv8i8 = truncate t2 ; CHECK: t5: v4i8 = extract_subvector t3, Constant:i64<0> -; CHECK: t7: v16i8 = insert_subvector undef:v16i8, t5, Constant:i64<0> +; CHECK: t7: v16i8 = insert_subvector poison:v16i8, t5, Constant:i64<0> ; CHECK: t9: ch,glue = CopyToReg t0, Register:v16i8 $q0, t7 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:v16i8 $q0, t9:1 @@ -69,7 +69,7 @@ define @insert_small_fixed_into_big_scalable(<8 x i8> %a) #0 ; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0 ; CHECK: t3: nxv8i8 = truncate t2 ; CHECK: t5: v4i8 = extract_subvector t3, Constant:i64<0> -; CHECK: t7: v16i8 = insert_subvector undef:v16i8, t5, Constant:i64<0> +; CHECK: t7: v16i8 = insert_subvector poison:v16i8, t5, Constant:i64<0> ; CHECK: t9: ch,glue = CopyToReg t0, Register:v16i8 $q0, t7 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:v16i8 $q0, t9:1 @@ -86,7 +86,7 @@ define <16 x i8> @insert_small_scalable_into_big_fixed( %a) #0 ; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0 ; CHECK: t3: nxv8i8 = truncate t2 ; CHECK: t5: v4i8 = extract_subvector t3, Constant:i64<0> -; CHECK: t7: nxv16i8 = insert_subvector undef:nxv16i8, t5, Constant:i64<0> +; CHECK: t7: nxv16i8 = insert_subvector poison:nxv16i8, t5, Constant:i64<0> ; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t7 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1 @@ -95,7 +95,7 @@ define <16 x i8> @insert_small_scalable_into_big_fixed( %a) #0 ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0 ; CHECK: t3: nxv8i8 = truncate t2 -; CHECK: t11: nxv16i8 = insert_subvector undef:nxv16i8, t3, Constant:i64<0> +; CHECK: t11: nxv16i8 = insert_subvector poison:nxv16i8, t3, Constant:i64<0> ; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t11 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1 @@ -111,7 +111,7 @@ define @insert_small_scalable_into_big_scalable_1( -; CHECK: t7: nxv16i8 = insert_subvector undef:nxv16i8, t5, Constant:i64<0> +; CHECK: t7: nxv16i8 = insert_subvector poison:nxv16i8, t5, Constant:i64<0> ; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t7 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1 @@ -120,7 +120,7 @@ define @insert_small_scalable_into_big_scalable_1( +; CHECK: t11: nxv16i8 = insert_subvector poison:nxv16i8, t3, Constant:i64<0> ; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t11 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1 @@ -135,7 +135,7 @@ define @insert_small_scalable_into_big_scalable_2( -; CHECK: t6: v8i8 = insert_subvector undef:v8i8, t4, Constant:i64<0> +; CHECK: t6: v8i8 = insert_subvector poison:v8i8, t4, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:v8i8 $d0, t6 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v8i8 $d0, t8:1 @@ -158,7 +158,7 @@ define <8 x i8> @extract_small_fixed_from_big_fixed(<16 x i8> %a) #0 { ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0 ; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0> -; CHECK: t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0> +; CHECK: t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0> ; CHECK: t7: nxv8i16 = any_extend t6 ; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1 @@ -168,7 +168,7 @@ define <8 x i8> @extract_small_fixed_from_big_fixed(<16 x i8> %a) #0 { ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0 ; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0> -; CHECK: t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0> +; CHECK: t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0> ; CHECK: t7: nxv8i16 = any_extend t6 ; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1 @@ -185,7 +185,7 @@ define @extract_small_scalable_from_big_fixed(<16 x i8> %a) #0 ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0 ; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0> -; CHECK: t6: v8i8 = insert_subvector undef:v8i8, t4, Constant:i64<0> +; CHECK: t6: v8i8 = insert_subvector poison:v8i8, t4, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:v8i8 $d0, t6 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v8i8 $d0, t8:1 @@ -208,7 +208,7 @@ define <8 x i8> @extract_small_fixed_from_big_scalable( %a) #0 ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0 ; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0> -; CHECK: t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0> +; CHECK: t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0> ; CHECK: t7: nxv8i16 = any_extend t6 ; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1 @@ -233,7 +233,7 @@ define @extract_small_scalable_from_big_scalable_1( -; CHECK: t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0> +; CHECK: t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0> ; CHECK: t7: nxv8i16 = any_extend t6 ; CHECK: t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7 ; CHECK: t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1 @@ -258,7 +258,7 @@ define @extract_small_scalable_from_big_scalable_2( -; CHECK: t6: v16i8 = insert_subvector undef:v16i8, t4, Constant:i64<0> +; CHECK: t6: v16i8 = insert_subvector poison:v16i8, t4, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t6 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1 @@ -285,7 +285,7 @@ define <16 x i8> @extract_fixed_from_scalable( %a) #0 { ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0 ; CHECK: t4: v4i8 = extract_subvector t2, Constant:i64<0> -; CHECK: t6: nxv16i8 = insert_subvector undef:nxv16i8, t4, Constant:i64<0> +; CHECK: t6: nxv16i8 = insert_subvector poison:nxv16i8, t4, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t6 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1 @@ -293,7 +293,7 @@ define <16 x i8> @extract_fixed_from_scalable( %a) #0 { ; CHECK: SelectionDAG has 9 nodes: ; CHECK: t0: ch,glue = EntryToken ; CHECK: t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0 -; CHECK: t10: nxv16i8 = insert_subvector undef:nxv16i8, t2, Constant:i64<0> +; CHECK: t10: nxv16i8 = insert_subvector poison:nxv16i8, t2, Constant:i64<0> ; CHECK: t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t10 ; CHECK: t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1 From a9f0e584ab873ceacffc04cecb771f401acbd28b Mon Sep 17 00:00:00 2001 From: zhijian Date: Fri, 21 Mar 2025 15:13:44 +0000 Subject: [PATCH 6/8] delete unused code --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 983297251e856..b62cf08693f63 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -697,9 +697,6 @@ END_TWO_BYTE_PACK() return NodeType == ISD::UNDEF || NodeType == ISD::POISON; } - /// Return true if the type of the node type poison. - bool isPoison() const { return NodeType == ISD::POISON; } - /// Test if this node is a memory intrinsic (with valid pointer information). bool isMemIntrinsic() const { return SDNodeBits.IsMemIntrinsic; } From f905090a7f69cbe9616e7d53db555e343d796800 Mon Sep 17 00:00:00 2001 From: zhijian Date: Thu, 27 Mar 2025 15:07:27 +0000 Subject: [PATCH 7/8] address comment --- llvm/include/llvm/CodeGen/SelectionDAG.h | 4 ++-- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 1 - llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index 956e5daa52131..ee5369df0f0ad 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1130,8 +1130,8 @@ class SelectionDAG { return getNode(ISD::UNDEF, SDLoc(), VT); } - /// Return an POISON node. POISON does not have a useful SDLoc. - SDValue getPoison(EVT VT) { return getNode(ISD::POISON, SDLoc(), VT); } + /// Return a POISON node. POISON does not have a useful SDLoc. + SDValue getPOISON(EVT VT) { return getNode(ISD::POISON, SDLoc(), VT); } /// Return a node that represents the runtime scaling 'MulImm * RuntimeVL'. SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index ea7e57c88a788..bc173326dd39b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -984,7 +984,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { // Additionally, many existing test cases rely on the current behavior (e.g., // llvm/test/CodeGen/PowerPC/vec_shuffle.ll). A broader discussion and // incremental changes might be needed to properly - // support POISON without breaking existing targets and tests. + // support POISON without breaking existing targets and tests. case ISD::POISON: { SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0)); ReplaceNode(Node, UndefNode.getNode()); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 5a03bc3eaed56..58ea971fe7f86 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -9203,7 +9203,6 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, SDVTList VTs = Indexed ? getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); - SDValue Ops[] = { Chain, Ptr, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::LOAD, VTs, Ops); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 77d8faeed7bc1..717ec02ef34d5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -1817,7 +1817,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { return DAG.getConstantFP(*CFP, getCurSDLoc(), VT); if (isa(C) && !V->getType()->isAggregateType()) - return isa(C) ? DAG.getPoison(VT) : DAG.getUNDEF(VT); + return isa(C) ? DAG.getPOISON(VT) : DAG.getUNDEF(VT); if (const ConstantExpr *CE = dyn_cast(C)) { visit(CE->getOpcode(), *CE); From 2eaa9791ebdcc623d89063753eaf6173ce632984 Mon Sep 17 00:00:00 2001 From: zhijian Date: Tue, 1 Apr 2025 15:56:46 +0000 Subject: [PATCH 8/8] address comment --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++-- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 3c92d9d8c7b7d..038114f383484 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -16266,8 +16266,8 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { // Finally, recreate the node, it's operands were updated to use // frozen operands, so we just need to use it's "original" operands. SmallVector Ops(N0->ops()); - // Special-handle ISD::UNDEF, ISD::POISON, each single one of them can be it's - // own thing. + // TODO: ISD::UNDEF and ISD::POISON should get separate handling, but best + // leave for a future patch. for (SDValue &Op : Ops) { if (Op.isUndef()) Op = DAG.getFreeze(Op); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 58ea971fe7f86..25ac0b956872e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -6262,7 +6262,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, if (N1.isUndef()) // sext(undef) = 0, because the top bits will all be the same. return getConstant(0, DL, VT); - break; case ISD::ZERO_EXTEND: assert(VT.isInteger() && N1.getValueType().isInteger() &&