diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 2c6b8828d5cfb..67bad5884c260 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -63,7 +63,7 @@ ModulePass * createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr); ModulePass *createAMDGPULowerBufferFatPointersPass(); FunctionPass *createSIModeRegisterPass(); -FunctionPass *createGCNPreRAOptimizationsPass(); +FunctionPass *createGCNPreRAOptimizationsLegacyPass(); FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass(); struct AMDGPUSimplifyLibCallsPass : PassInfoMixin { @@ -454,7 +454,7 @@ extern char &GCNNSAReassignID; void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &); extern char &GCNPreRALongBranchRegID; -void initializeGCNPreRAOptimizationsPass(PassRegistry &); +void initializeGCNPreRAOptimizationsLegacyPass(PassRegistry &); extern char &GCNPreRAOptimizationsID; FunctionPass *createAMDGPUSetWavePriorityPass(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index 41ad1445f47e9..d9d97928062f5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -98,6 +98,7 @@ FUNCTION_PASS_WITH_PARAMS( #endif MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this)) MACHINE_FUNCTION_PASS("amdgpu-pre-ra-long-branch-reg", GCNPreRALongBranchRegPass()) +MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()) MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass()) MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass()) MACHINE_FUNCTION_PASS("si-fix-vgpr-copies", SIFixVGPRCopiesPass()) @@ -118,7 +119,6 @@ MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass()) #define DUMMY_MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-insert-delay-alu", AMDGPUInsertDelayAluPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass()) -DUMMY_MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass()) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index fffd30b26dc1d..3dfa33578243c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -33,6 +33,7 @@ #include "GCNDPPCombine.h" #include "GCNIterativeScheduler.h" #include "GCNPreRALongBranchReg.h" +#include "GCNPreRAOptimizations.h" #include "GCNSchedStrategy.h" #include "GCNVOPDUtils.h" #include "R600.h" @@ -548,7 +549,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeAMDGPUPrintfRuntimeBindingPass(*PR); initializeAMDGPUResourceUsageAnalysisPass(*PR); initializeGCNNSAReassignPass(*PR); - initializeGCNPreRAOptimizationsPass(*PR); + initializeGCNPreRAOptimizationsLegacyPass(*PR); initializeGCNPreRALongBranchRegLegacyPass(*PR); initializeGCNRewritePartialRegUsesPass(*PR); initializeGCNRegPressurePrinterPass(*PR); diff --git a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp index a6112b39325ee..0f008f70a6c3d 100644 --- a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp +++ b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp @@ -24,6 +24,7 @@ /// //===----------------------------------------------------------------------===// +#include "GCNPreRAOptimizations.h" #include "AMDGPU.h" #include "GCNSubtarget.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" @@ -37,7 +38,7 @@ using namespace llvm; namespace { -class GCNPreRAOptimizations : public MachineFunctionPass { +class GCNPreRAOptimizationsImpl { private: const SIInstrInfo *TII; const SIRegisterInfo *TRI; @@ -46,11 +47,17 @@ class GCNPreRAOptimizations : public MachineFunctionPass { bool processReg(Register Reg); +public: + GCNPreRAOptimizationsImpl(LiveIntervals *LS) : LIS(LS) {} + bool run(MachineFunction &MF); +}; + +class GCNPreRAOptimizationsLegacy : public MachineFunctionPass { public: static char ID; - GCNPreRAOptimizations() : MachineFunctionPass(ID) { - initializeGCNPreRAOptimizationsPass(*PassRegistry::getPassRegistry()); + GCNPreRAOptimizationsLegacy() : MachineFunctionPass(ID) { + initializeGCNPreRAOptimizationsLegacyPass(*PassRegistry::getPassRegistry()); } bool runOnMachineFunction(MachineFunction &MF) override; @@ -65,24 +72,23 @@ class GCNPreRAOptimizations : public MachineFunctionPass { MachineFunctionPass::getAnalysisUsage(AU); } }; - } // End anonymous namespace. -INITIALIZE_PASS_BEGIN(GCNPreRAOptimizations, DEBUG_TYPE, +INITIALIZE_PASS_BEGIN(GCNPreRAOptimizationsLegacy, DEBUG_TYPE, "AMDGPU Pre-RA optimizations", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_END(GCNPreRAOptimizations, DEBUG_TYPE, "Pre-RA optimizations", - false, false) +INITIALIZE_PASS_END(GCNPreRAOptimizationsLegacy, DEBUG_TYPE, + "Pre-RA optimizations", false, false) -char GCNPreRAOptimizations::ID = 0; +char GCNPreRAOptimizationsLegacy::ID = 0; -char &llvm::GCNPreRAOptimizationsID = GCNPreRAOptimizations::ID; +char &llvm::GCNPreRAOptimizationsID = GCNPreRAOptimizationsLegacy::ID; -FunctionPass *llvm::createGCNPreRAOptimizationsPass() { - return new GCNPreRAOptimizations(); +FunctionPass *llvm::createGCNPreRAOptimizationsLegacyPass() { + return new GCNPreRAOptimizationsLegacy(); } -bool GCNPreRAOptimizations::processReg(Register Reg) { +bool GCNPreRAOptimizationsImpl::processReg(Register Reg) { MachineInstr *Def0 = nullptr; MachineInstr *Def1 = nullptr; uint64_t Init = 0; @@ -212,14 +218,25 @@ bool GCNPreRAOptimizations::processReg(Register Reg) { return true; } -bool GCNPreRAOptimizations::runOnMachineFunction(MachineFunction &MF) { +bool GCNPreRAOptimizationsLegacy::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; + LiveIntervals *LIS = &getAnalysis().getLIS(); + return GCNPreRAOptimizationsImpl(LIS).run(MF); +} + +PreservedAnalyses +GCNPreRAOptimizationsPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + LiveIntervals *LIS = &MFAM.getResult(MF); + GCNPreRAOptimizationsImpl(LIS).run(MF); + return PreservedAnalyses::all(); +} +bool GCNPreRAOptimizationsImpl::run(MachineFunction &MF) { const GCNSubtarget &ST = MF.getSubtarget(); TII = ST.getInstrInfo(); MRI = &MF.getRegInfo(); - LIS = &getAnalysis().getLIS(); TRI = ST.getRegisterInfo(); bool Changed = false; diff --git a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.h b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.h new file mode 100644 index 0000000000000..295152b64b4c6 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.h @@ -0,0 +1,23 @@ +//===- GCNPreRAOptimizations.h ----------------------------------*- C++- *-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AMDGPU_GCNPRERAOPTIMIZATIONS_H +#define LLVM_LIB_TARGET_AMDGPU_GCNPRERAOPTIMIZATIONS_H + +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { +class GCNPreRAOptimizationsPass + : public PassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; +} // namespace llvm + +#endif // LLVM_LIB_TARGET_AMDGPU_GCNPRERAOPTIMIZATIONS_H diff --git a/llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir b/llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir index 86a1a26cb7abf..6eb5b7bad166d 100644 --- a/llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=liveintervals,amdgpu-pre-ra-optimizations -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX908 %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=amdgpu-pre-ra-optimizations -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX908 %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes="amdgpu-pre-ra-optimizations" %s -o - | FileCheck -check-prefix=GFX908 %s --- name: test_mfma_f32_4x4x1f32_propagate_vgpr diff --git a/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir b/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir index 57afb456d6037..4f4b5b121ace6 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir +++ b/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=liveintervals,amdgpu-pre-ra-optimizations %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=amdgpu-pre-ra-optimizations %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -passes="amdgpu-pre-ra-optimizations" %s -o - | FileCheck -check-prefix=GCN %s --- name: combine_sreg64_inits