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[RISCV] Allow undef prefix for local repeating VLA shuffle lowering #126097

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Merged
merged 2 commits into from
Feb 11, 2025
Merged

[RISCV] Allow undef prefix for local repeating VLA shuffle lowering #126097

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ab283cb
[RISCV] Allow undef prefix for local repeating VLA shuffle lowering
preames Feb 6, 2025
842f798
Address review comment
preames Feb 11, 2025
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17 changes: 11 additions & 6 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5338,13 +5338,19 @@ static SDValue lowerDisjointIndicesShuffle(ShuffleVectorSDNode *SVN,
/// Is this mask local (i.e. elements only move within their local span), and
/// repeating (that is, the same rearrangement is being done within each span)?
static bool isLocalRepeatingShuffle(ArrayRef<int> Mask, int Span) {
// TODO: Could improve the case where undef elements exist in the first span.
SmallVector<int> LowSpan(Span, -1);
for (auto [I, M] : enumerate(Mask)) {
if (M == -1)
continue;
int ChunkLo = I - (I % Span);
int SpanIdx = I % Span;
int ChunkLo = I - SpanIdx;
int ChunkHi = ChunkLo + Span;
if (M < ChunkLo || M >= ChunkHi || M - ChunkLo != Mask[I % Span])
if (M < ChunkLo || M >= ChunkHi)
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@topperc topperc Feb 11, 2025

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This can be simplified to

if ((M / Span) != (I / Span))
  return false;
int Expected = M % Span;

return false;
int Expected = M - ChunkLo;
if (LowSpan[SpanIdx] == -1)
LowSpan[SpanIdx] = Expected;
if (LowSpan[SpanIdx] != Expected)
return false;
}
return true;
Expand Down Expand Up @@ -5742,9 +5748,8 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
// If we have a locally repeating mask, then we can reuse the first register
// in the index register group for all registers within the source register
// group. TODO: This generalizes to m2, and m4.
const MVT M1VT = getLMUL1VT(ContainerVT);
auto VLMAX = RISCVTargetLowering::computeVLMAXBounds(M1VT, Subtarget).first;
if (ContainerVT.bitsGT(M1VT) && isLocalRepeatingShuffle(Mask, VLMAX)) {
if (NumElts > MinVLMAX && isLocalRepeatingShuffle(Mask, MinVLMAX)) {
const MVT M1VT = getLMUL1VT(ContainerVT);
EVT SubIndexVT = M1VT.changeVectorElementType(IndexVT.getScalarType());
SDValue SubIndex =
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubIndexVT, LHSIndices,
Expand Down
49 changes: 41 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
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Expand Up @@ -969,11 +969,44 @@ define <8 x i64> @shuffle_v8i64_as_i128(<8 x i64> %v) {
ret <8 x i64> %shuffle
}

define <8 x i64> @shuffle_v8i64_as_i256(<8 x i64> %v) {
; CHECK-LABEL: shuffle_v8i64_as_i256:
; Test case where first span has undefs
define <8 x i64> @shuffle_v8i64_as_i128_2(<8 x i64> %v) {
; CHECK-LABEL: shuffle_v8i64_as_i128_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI30_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI30_0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vrgatherei16.vv v13, v9, v16
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
; CHECK-NEXT: vrgatherei16.vv v14, v10, v16
; CHECK-NEXT: vrgatherei16.vv v15, v11, v16
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
;
; ZVKB-V-LABEL: shuffle_v8i64_as_i128_2:
; ZVKB-V: # %bb.0:
; ZVKB-V-NEXT: lui a0, %hi(.LCPI30_0)
; ZVKB-V-NEXT: addi a0, a0, %lo(.LCPI30_0)
; ZVKB-V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVKB-V-NEXT: vle16.v v16, (a0)
; ZVKB-V-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; ZVKB-V-NEXT: vrgatherei16.vv v13, v9, v16
; ZVKB-V-NEXT: vrgatherei16.vv v12, v8, v16
; ZVKB-V-NEXT: vrgatherei16.vv v14, v10, v16
; ZVKB-V-NEXT: vrgatherei16.vv v15, v11, v16
; ZVKB-V-NEXT: vmv4r.v v8, v12
; ZVKB-V-NEXT: ret
%shuffle = shufflevector <8 x i64> %v, <8 x i64> poison, <8 x i32> <i32 undef, i32 undef, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i64> %shuffle
}

define <8 x i64> @shuffle_v8i64_as_i256(<8 x i64> %v) {
; CHECK-LABEL: shuffle_v8i64_as_i256:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI31_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI31_0)
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
Expand All @@ -982,8 +1015,8 @@ define <8 x i64> @shuffle_v8i64_as_i256(<8 x i64> %v) {
;
; ZVKB-V-LABEL: shuffle_v8i64_as_i256:
; ZVKB-V: # %bb.0:
; ZVKB-V-NEXT: lui a0, %hi(.LCPI30_0)
; ZVKB-V-NEXT: addi a0, a0, %lo(.LCPI30_0)
; ZVKB-V-NEXT: lui a0, %hi(.LCPI31_0)
; ZVKB-V-NEXT: addi a0, a0, %lo(.LCPI31_0)
; ZVKB-V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; ZVKB-V-NEXT: vle16.v v16, (a0)
; ZVKB-V-NEXT: vrgatherei16.vv v12, v8, v16
Expand All @@ -996,8 +1029,8 @@ define <8 x i64> @shuffle_v8i64_as_i256(<8 x i64> %v) {
define <8 x i64> @shuffle_v8i64_as_i256_zvl256b(<8 x i64> %v) vscale_range(4,0) {
; CHECK-LABEL: shuffle_v8i64_as_i256_zvl256b:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI31_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI31_0)
; CHECK-NEXT: lui a0, %hi(.LCPI32_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI32_0)
; CHECK-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
Expand All @@ -1008,8 +1041,8 @@ define <8 x i64> @shuffle_v8i64_as_i256_zvl256b(<8 x i64> %v) vscale_range(4,0)
;
; ZVKB-V-LABEL: shuffle_v8i64_as_i256_zvl256b:
; ZVKB-V: # %bb.0:
; ZVKB-V-NEXT: lui a0, %hi(.LCPI31_0)
; ZVKB-V-NEXT: addi a0, a0, %lo(.LCPI31_0)
; ZVKB-V-NEXT: lui a0, %hi(.LCPI32_0)
; ZVKB-V-NEXT: addi a0, a0, %lo(.LCPI32_0)
; ZVKB-V-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
; ZVKB-V-NEXT: vle16.v v12, (a0)
; ZVKB-V-NEXT: vsetvli a0, zero, e64, m1, ta, ma
Expand Down
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