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Merged
lenary merged 2 commits into from
Feb 11, 2025
Merged

[RISCV] Improve Errors for GPRNoX0 Reg Class #126397

lenary merged 2 commits into from
Feb 11, 2025

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@lenary lenary commented Feb 9, 2025

More adoption of better diagnostics for RISC-V register classes:

  • GPRNoX0 (GPRs excluding zero)

@lenary
[RISCV] Improve Errors for GPRNoX0 Reg Class
dedeb44 
More adoption of better diagnostics for RISC-V register classes:
- GPRNoX0 (GPRs excluding `zero`)
@llvmbot llvmbot added backend:RISC-V llvm:mc Machine (object) code labels Feb 9, 2025
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llvmbot commented Feb 9, 2025 •
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@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

More adoption of better diagnostics for RISC-V register classes:

  • GPRNoX0 (GPRs excluding zero)

Patch is 51.12 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/126397.diff

15 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.td (+4-1)
  • (modified) llvm/test/MC/RISCV/rv32c-invalid.s (+5-5)
  • (modified) llvm/test/MC/RISCV/rv32zicfiss-invalid.s (+1-1)
  • (modified) llvm/test/MC/RISCV/rv64c-invalid.s (+2-2)
  • (modified) llvm/test/MC/RISCV/rv64zicfiss-invalid.s (+1-1)
  • (modified) llvm/test/MC/RISCV/rvc-hints-invalid.s (+2-2)
  • (modified) llvm/test/MC/RISCV/xqcia-invalid.s (+78-39)
  • (modified) llvm/test/MC/RISCV/xqciac-invalid.s (+6-3)
  • (modified) llvm/test/MC/RISCV/xqcicli-invalid.s (+60-30)
  • (modified) llvm/test/MC/RISCV/xqcicm-invalid.s (+26-13)
  • (modified) llvm/test/MC/RISCV/xqcics-invalid.s (+16-8)
  • (modified) llvm/test/MC/RISCV/xqcicsr-invalid.s (+4-2)
  • (modified) llvm/test/MC/RISCV/xqciint-invalid.s (+24-19)
  • (modified) llvm/test/MC/RISCV/xqcilsm-invalid.s (+8-4)
  • (modified) llvm/test/MC/RISCV/xqcisls-invalid.s (+32-16)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 7eb93973459c0d3..470ef9fbeb962ce 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -250,7 +250,10 @@ def GPRX0 : GPRRegisterClass<(add X0)>;
 def GPRX1 : GPRRegisterClass<(add X1)>;
 def GPRX5 : GPRRegisterClass<(add X5)>;
 
-def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>;
+def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)> {
+  let DiagnosticType = "InvalidRegClassGPRX0";
+  let DiagnosticString = "register must be a GPR excluding zero (x0)";
+}
 
 def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)>;
 
diff --git a/llvm/test/MC/RISCV/rv32c-invalid.s b/llvm/test/MC/RISCV/rv32c-invalid.s
index 9fbd5e9f117f988..111f2f7046d3832 100644
--- a/llvm/test/MC/RISCV/rv32c-invalid.s
+++ b/llvm/test/MC/RISCV/rv32c-invalid.s
@@ -19,15 +19,15 @@ c.xor  t2, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 c.sub  a0, s8 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
 
 ## GPRNoX0
-c.lwsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-c.lwsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-c.jr  x0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-c.jalr  zero # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.lwsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
+c.lwsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
+c.jr  x0 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding zero (x0)
+c.jalr  zero # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
 c.addi  x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero
 c.li  zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
 c.slli  zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
 c.mv  zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
-c.mv  ra, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+c.mv  ra, x0 # CHECK: :[[@LINE]]:11: error: register must be a GPR excluding zero (x0)
 c.add  ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
 c.add  zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
diff --git a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
index 048df67e8a6461b..e1de31ff42eb01c 100644
--- a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
@@ -13,5 +13,5 @@ c.sspopchk ra
 # CHECK-ERR: error: invalid operand for instruction
 sspush a0
 
-# CHECK-ERR: error: invalid operand for instruction
+# CHECK-ERR: error: register must be a GPR excluding zero (x0)
 ssrdp zero
diff --git a/llvm/test/MC/RISCV/rv64c-invalid.s b/llvm/test/MC/RISCV/rv64c-invalid.s
index aecc3b4d664ff6d..9b0a3244f3aacc8 100644
--- a/llvm/test/MC/RISCV/rv64c-invalid.s
+++ b/llvm/test/MC/RISCV/rv64c-invalid.s
@@ -8,8 +8,8 @@ c.addw   a0, a7 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 c.subw   a0, a6 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
 ## GPRNoX0
-c.ldsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-c.ldsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.ldsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
+c.ldsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
 
 # Out of range immediates
 
diff --git a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
index fc69c68a477d6cc..5be81d57abd589c 100644
--- a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
@@ -13,5 +13,5 @@ c.sspopchk ra
 # CHECK-ERR: error: invalid operand for instruction
 sspush a0
 
-# CHECK-ERR: error: invalid operand for instruction
+# CHECK-ERR: error: register must be a GPR excluding zero (x0)
 ssrdp zero
diff --git a/llvm/test/MC/RISCV/rvc-hints-invalid.s b/llvm/test/MC/RISCV/rvc-hints-invalid.s
index 50704010fc82a8e..2a7a6addd31abaf 100644
--- a/llvm/test/MC/RISCV/rvc-hints-invalid.s
+++ b/llvm/test/MC/RISCV/rvc-hints-invalid.s
@@ -11,9 +11,9 @@ c.li x0, 42 # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the r
 
 c.lui x0, 0 # CHECK: :[[@LINE]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]
 
-c.mv x0, x0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.mv x0, x0 # CHECK: :[[@LINE]]:10: error: register must be a GPR excluding zero (x0)
 
-c.add x0, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+c.add x0, x0 # CHECK: :[[@LINE]]:11: error: register must be a GPR excluding zero (x0)
 
 c.slli x0, 0 # CHECK-RV32: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
 c.slli x0, 32 # CHECK-RV32: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
diff --git a/llvm/test/MC/RISCV/xqcia-invalid.s b/llvm/test/MC/RISCV/xqcia-invalid.s
index a410fb63fad9c92..aa4d7143a4919de 100644
--- a/llvm/test/MC/RISCV/xqcia-invalid.s
+++ b/llvm/test/MC/RISCV/xqcia-invalid.s
@@ -4,143 +4,173 @@
 # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcia < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
 
-# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
 qc.slasat x10, x3, 17
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.slasat x10, x3
 
-# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
 qc.slasat x0, x3, x17
 
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
 qc.slasat x10, x0, x17
 
-# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
 qc.slasat x10, x3, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.slasat x10, x3, x17
 
 
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
 qc.sllsat x23, x25, 27
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.sllsat x23, x25
 
-# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
 qc.sllsat x0, x25, x27
 
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
 qc.sllsat x23, x0, x27
 
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
 qc.sllsat x23, x25, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.sllsat x23, x25, x27
 
 
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
 qc.addsat x17, x14, 7
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.addsat x17, x14
 
-# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
 qc.addsat x0, x14, x7
 
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
 qc.addsat x17, x0, x7
 
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
 qc.addsat x17, x14, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.addsat x17, x14, x7
 
 
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
 qc.addusat x8, x18, 28
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.addusat x8, x18
 
-# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
 qc.addusat x0, x18, x28
 
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
 qc.addusat x8, x0, x28
 
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
 qc.addusat x8, x18, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.addusat x8, x18, x28
 
 
-# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
 qc.subsat x22, x2, 12
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.subsat x22, x2
 
-# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
 qc.subsat x0, x2, x12
 
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
 qc.subsat x22, x0, x12
 
-# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
 qc.subsat x22, x2, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.subsat x22, x2, x12
 
 
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
 qc.subusat x9, x14, 17
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.subusat x9, x14
 
-# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
 qc.subusat x0, x14, x17
 
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
 qc.subusat x9, x0, x17
 
-# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
 qc.subusat x9, x14, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.subusat x9, x14, x17
 
 
-# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction
 qc.wrap x3, x30, 23
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.wrap x3, x30
 
-# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction
 qc.wrap x0, x30, x23
 
-# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction
 qc.wrap x3, x30, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.wrap x3, x30, x23
 
 
-# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction
 qc.wrapi x0, 12, 2047
 
-# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction
 qc.wrapi x0, x12, 2047
 
-# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction
 qc.wrapi x6, x0, 2047
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
@@ -153,48 +183,57 @@ qc.wrapi x6, x12, 2048
 qc.wrapi x6, x12, 2047
 
 
-# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction
 qc.norm x3, 7
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.norm x3
 
-# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction
 qc.norm x0, x7
 
-# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction
 qc.norm x3, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.norm x3, x7
 
 
-# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction
 qc.normu x11, 17
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.normu x11
 
-# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction
 qc.normu x0, x17
 
-# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction
 qc.normu x11, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
 qc.normu x11, x17
 
 
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
 qc.normeu x26, 31
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
 qc.normeu x26
 
-# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
 qc.normeu x0, x31
 
-# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
 qc.normeu x26, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
diff --git a/llvm/test/MC/RISCV/xqciac-invalid.s b/llvm/test/MC/RISCV/xqciac-invalid.s
index c595888ddee3e82..3f2d8733b703201 100644
--- a/llvm/test/MC/RISCV/xqciac-invalid.s
+++ b/llvm/test/MC/RISCV/xqciac-invalid.s
@@ -4,7 +4,8 @@
 # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciac < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-EXT %s
 
-# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction
 qc.c.muliadd x5, x10, 4
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
@@ -17,7 +18,8 @@ qc.c.muliadd x10, x15, 32
 qc.c.muliadd x10, x15, 20
 
 
-# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
 qc.muliadd x0, x10, 1048577
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
@@ -30,7 +32,8 @@ qc.muliadd x10, x15, 8589934592
 qc.muliadd x10, x15, 577
 
 
-# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
 qc.shladd 0, x10, 1048577
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/xqcicli-invalid.s b/llvm/test/MC/RISCV/xqcicli-invalid.s
index 7ee92ec4cbc0123..a2f5549a394f497 100644
--- a/llvm/test/MC/RISCV/xqcicli-invalid.s
+++ b/llvm/test/MC/RISCV/xqcicli-invalid.s
@@ -4,13 +4,16 @@
 # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicli < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
 
-# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction
 qc.lieq x0, x4, x6, 10
 
-# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction
 qc.lieq x2, x0, x6, 10
 
-# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction
 qc.lieq x2, x4, x0, 10
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
@@ -23,13 +26,16 @@ qc.lieq x2, x4, x6, 40
 qc.lieq x2, x4, x6, 10
 
 
-# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction
 qc.lige x0, x8, x20, 2
 
-# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
+# CHECK-PLUS: :[[@LINE+2]]:13: ...
[truncated]

wangpc-pp
wangpc-pp approved these changes Feb 10, 2025
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LGTM.

topperc
topperc approved these changes Feb 10, 2025
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LGTM

@lenary lenary merged commit ea6827c into llvm:main Feb 11, 2025
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@lenary lenary deleted the pr/riscv-reg-errors-3 branch February 11, 2025 01:21
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llvm-ci commented Feb 11, 2025

LLVM Buildbot has detected a new failure on builder clang-cmake-x86_64-avx512-win running on avx512-intel64-win while building llvm at step 6 "ninja check 1".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/81/builds/4602

Here is the relevant piece of the build log for the reference 
Step 6 (ninja check 1) failure: stage 1 checked (failure)
******************** TEST 'Clang :: Driver/offload-Xarch.c' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 3
d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe --target=x86_64-unknown-linux-gnu -x cuda D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c -Xarch_nvptx64 -O3 -S -nogpulib -nogpuinc -### 2>&1 | d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe -check-prefix=O3ONCE D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe' --target=x86_64-unknown-linux-gnu -x cuda 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c' -Xarch_nvptx64 -O3 -S -nogpulib -nogpuinc '-###'
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe' -check-prefix=O3ONCE 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# RUN: at line 4
d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe -x cuda D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c -Xarch_device -O3 -S -nogpulib -nogpuinc -### 2>&1 | d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe -check-prefix=O3ONCE D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe' -x cuda 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c' -Xarch_device -O3 -S -nogpulib -nogpuinc '-###'
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe' -check-prefix=O3ONCE 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# RUN: at line 5
d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe -x hip D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c -Xarch_amdgcn -O3 -S -nogpulib -nogpuinc -### 2>&1 | d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe -check-prefix=O3ONCE D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe' -x hip 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c' -Xarch_amdgcn -O3 -S -nogpulib -nogpuinc '-###'
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe' -check-prefix=O3ONCE 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# RUN: at line 6
d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -nogpulib -nogpuinc    -Xarch_amdgcn -march=gfx90a -Xarch_amdgcn -O3 -S -### D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c 2>&1  | d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe -check-prefix=O3ONCE D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe' -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -nogpulib -nogpuinc -Xarch_amdgcn -march=gfx90a -Xarch_amdgcn -O3 -S '-###' 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe' -check-prefix=O3ONCE 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# RUN: at line 9
d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe -fopenmp=libomp -fopenmp-targets=nvptx64-nvidia-cuda -nogpulib -nogpuinc    -Xarch_nvptx64 -march=sm_52 -Xarch_nvptx64 -O3 -S -### D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c 2>&1  | d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe -check-prefix=O3ONCE D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe' -fopenmp=libomp -fopenmp-targets=nvptx64-nvidia-cuda -nogpulib -nogpuinc -Xarch_nvptx64 -march=sm_52 -Xarch_nvptx64 -O3 -S '-###' 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe' -check-prefix=O3ONCE 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# RUN: at line 15
d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe -fopenmp=libomp -fopenmp-targets=nvptx64-nvidia-cuda,amdgcn-amd-amdhsa -nogpulib    --target=x86_64-unknown-linux-gnu -Xopenmp-target=nvptx64-nvidia-cuda --offload-arch=sm_52,sm_60 -nogpuinc    -Xopenmp-target=amdgcn-amd-amdhsa --offload-arch=gfx90a,gfx1030 -ccc-print-bindings -### D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c 2>&1  | d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe -check-prefix=OPENMP D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe' -fopenmp=libomp -fopenmp-targets=nvptx64-nvidia-cuda,amdgcn-amd-amdhsa -nogpulib --target=x86_64-unknown-linux-gnu -Xopenmp-target=nvptx64-nvidia-cuda --offload-arch=sm_52,sm_60 -nogpuinc -Xopenmp-target=amdgcn-amd-amdhsa --offload-arch=gfx90a,gfx1030 -ccc-print-bindings '-###' 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe' -check-prefix=OPENMP 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# RUN: at line 31
d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe -x cuda D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c --offload-arch=sm_52,sm_60 -Xarch_sm_52 -O3 -Xarch_sm_60 -O0    --target=x86_64-unknown-linux-gnu -Xarch_host -O3 -S -nogpulib -nogpuinc -### 2>&1  | d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe -check-prefix=CUDA D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe' -x cuda 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c' --offload-arch=sm_52,sm_60 -Xarch_sm_52 -O3 -Xarch_sm_60 -O0 --target=x86_64-unknown-linux-gnu -Xarch_host -O3 -S -nogpulib -nogpuinc '-###'
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe' -check-prefix=CUDA 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# RUN: at line 39
d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe -fopenmp=libomp --offload-arch=gfx90a -nogpulib -nogpuinc    --target=x86_64-unknown-linux-gnu -Xarch_amdgcn -Wl,-lfoo -### D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c 2>&1  | d:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe -check-prefix=LIBS D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\clang.exe' -fopenmp=libomp --offload-arch=gfx90a -nogpulib -nogpuinc --target=x86_64-unknown-linux-gnu -Xarch_amdgcn -Wl,-lfoo '-###' 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# executed command: 'd:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\stage1\bin\filecheck.exe' -check-prefix=LIBS 'D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c'
# .---command stderr------------
# | D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c:45:10: error: LIBS: expected string not found in input
# | // LIBS: "--device-linker=amdgcn-amd-amdhsa=-lfoo"
# |          ^
# | <stdin>:1:1: note: scanning from here
# | clang version 21.0.0git (https://github.com/llvm/llvm-project.git ea6827cacfde062c7d9f03266af5298499313176)
# | ^
# | <stdin>:6:1436: note: possible intended match here
# |  "D:\\buildbot\\llvm-worker\\clang-cmake-x86_64-avx512-win\\stage1\\bin\\clang.exe" "-cc1" "-triple" "x86_64-unknown-linux-gnu" "-emit-llvm-bc" "-emit-llvm-uselists" "-dumpdir" "a-" "-disable-free" "-clear-ast-before-backend" "-main-file-name" "offload-Xarch.c" "-mrelocation-model" "pic" "-pic-level" "2" "-pic-is-pie" "-mframe-pointer=all" "-fmath-errno" "-ffp-contract=on" "-fno-rounding-math" "-mconstructor-aliases" "-funwind-tables=2" "-target-cpu" "x86-64" "-tune-cpu" "generic" "-debugger-tuning=gdb" "-fdebug-compilation-dir=D:\\buildbot\\llvm-worker\\clang-cmake-x86_64-avx512-win\\stage1\\tools\\clang\\test\\Driver" "-fcoverage-compilation-dir=D:\\buildbot\\llvm-worker\\clang-cmake-x86_64-avx512-win\\stage1\\tools\\clang\\test\\Driver" "-resource-dir" "D:\\buildbot\\llvm-worker\\clang-cmake-x86_64-avx512-win\\stage1\\lib\\clang\\21" "-internal-isystem" "D:\\buildbot\\llvm-worker\\clang-cmake-x86_64-avx512-win\\stage1\\lib\\clang\\21\\include" "-internal-isystem" "/usr/local/include" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-internal-isystem" "D:\\buildbot\\llvm-worker\\clang-cmake-x86_64-avx512-win\\stage1\\lib\\clang\\21\\include" "-internal-isystem" "/usr/local/include" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-ferror-limit" "19" "-fopenmp" "-nogpulib" "-fgnuc-version=4.2.1" "-fskip-odr-check-in-gmf" "-disable-llvm-passes" "-fopenmp-targets=amdgcn-amd-amdhsa" "-faddrsig" "-D__GCC_HAVE_DWARF2_CFI_ASM=1" "-o" "C:\\Users\\tianfei\\AppData\\Local\\Temp\\1\\lit-tmp-okzhkxof\\offload-Xarch-08d255.bc" "-x" "c" "D:\\buildbot\\llvm-worker\\clang-cmake-x86_64-avx512-win\\llvm\\clang\\test\\Driver\\offload-Xarch.c"
# |                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ^
# | 
# | Input file: <stdin>
# | Check file: D:\buildbot\llvm-worker\clang-cmake-x86_64-avx512-win\llvm\clang\test\Driver\offload-Xarch.c
...

Icohedron pushed a commit to Icohedron/llvm-project that referenced this pull request Feb 11, 2025
@lenary @Icohedron
[RISCV] Improve Errors for GPRNoX0 Reg Class (llvm#126397)
504f7d9 
More adoption of better diagnostics for RISC-V register classes:
- GPRNoX0 (GPRs excluding `zero`)
joaosaffran pushed a commit to joaosaffran/llvm-project that referenced this pull request Feb 14, 2025
@lenary
[RISCV] Improve Errors for GPRNoX0 Reg Class (llvm#126397)
bcc2cde 
More adoption of better diagnostics for RISC-V register classes:
- GPRNoX0 (GPRs excluding `zero`)
sivan-shani pushed a commit to sivan-shani/llvm-project that referenced this pull request Feb 24, 2025
@lenary @sivan-shani
[RISCV] Improve Errors for GPRNoX0 Reg Class (llvm#126397)
7fccd54 
More adoption of better diagnostics for RISC-V register classes:
- GPRNoX0 (GPRs excluding `zero`)
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