diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 6f2d0cf40352f..a5dfb5ba1a2fc 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -258,7 +258,10 @@ def GPRX5 : GPRRegisterClass<(add X5)> { let DiagnosticString = "register must be t0 (x5)"; } -def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>; +def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)> { + let DiagnosticType = "InvalidRegClassGPRX0"; + let DiagnosticString = "register must be a GPR excluding zero (x0)"; +} def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)> { let DiagnosticType = "InvalidRegClassGPRNoX0X2"; diff --git a/llvm/test/MC/RISCV/rv32c-invalid.s b/llvm/test/MC/RISCV/rv32c-invalid.s index d618a13ca4047..1027c08505d50 100644 --- a/llvm/test/MC/RISCV/rv32c-invalid.s +++ b/llvm/test/MC/RISCV/rv32c-invalid.s @@ -19,15 +19,15 @@ c.xor t2, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction c.sub a0, s8 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction ## GPRNoX0 -c.lwsp x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction -c.lwsp zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction -c.jr x0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction -c.jalr zero # CHECK: :[[@LINE]]:9: error: invalid operand for instruction +c.lwsp x0, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0) +c.lwsp zero, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0) +c.jr x0 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding zero (x0) +c.jalr zero # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0) c.addi x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}} c.slli zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}} -c.mv ra, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction +c.mv ra, x0 # CHECK: :[[@LINE]]:11: error: register must be a GPR excluding zero (x0) c.add ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction c.add zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64c-invalid.s b/llvm/test/MC/RISCV/rv64c-invalid.s index aecc3b4d664ff..9b0a3244f3aac 100644 --- a/llvm/test/MC/RISCV/rv64c-invalid.s +++ b/llvm/test/MC/RISCV/rv64c-invalid.s @@ -8,8 +8,8 @@ c.addw a0, a7 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction c.subw a0, a6 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction ## GPRNoX0 -c.ldsp x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction -c.ldsp zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction +c.ldsp x0, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0) +c.ldsp zero, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0) # Out of range immediates diff --git a/llvm/test/MC/RISCV/rvc-hints-invalid.s b/llvm/test/MC/RISCV/rvc-hints-invalid.s index 50704010fc82a..2a7a6addd31ab 100644 --- a/llvm/test/MC/RISCV/rvc-hints-invalid.s +++ b/llvm/test/MC/RISCV/rvc-hints-invalid.s @@ -11,9 +11,9 @@ c.li x0, 42 # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the r c.lui x0, 0 # CHECK: :[[@LINE]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31] -c.mv x0, x0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction +c.mv x0, x0 # CHECK: :[[@LINE]]:10: error: register must be a GPR excluding zero (x0) -c.add x0, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction +c.add x0, x0 # CHECK: :[[@LINE]]:11: error: register must be a GPR excluding zero (x0) c.slli x0, 0 # CHECK-RV32: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31] c.slli x0, 32 # CHECK-RV32: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31] diff --git a/llvm/test/MC/RISCV/xqcia-invalid.s b/llvm/test/MC/RISCV/xqcia-invalid.s index a410fb63fad9c..aa4d7143a4919 100644 --- a/llvm/test/MC/RISCV/xqcia-invalid.s +++ b/llvm/test/MC/RISCV/xqcia-invalid.s @@ -4,143 +4,173 @@ # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcia < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s -# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction qc.slasat x10, x3, 17 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.slasat x10, x3 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.slasat x0, x3, x17 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.slasat x10, x0, x17 -# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction qc.slasat x10, x3, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.slasat x10, x3, x17 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.sllsat x23, x25, 27 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.sllsat x23, x25 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.sllsat x0, x25, x27 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.sllsat x23, x0, x27 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.sllsat x23, x25, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.sllsat x23, x25, x27 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.addsat x17, x14, 7 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.addsat x17, x14 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.addsat x0, x14, x7 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.addsat x17, x0, x7 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.addsat x17, x14, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.addsat x17, x14, x7 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.addusat x8, x18, 28 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.addusat x8, x18 -# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction qc.addusat x0, x18, x28 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.addusat x8, x0, x28 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.addusat x8, x18, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.addusat x8, x18, x28 -# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction qc.subsat x22, x2, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.subsat x22, x2 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.subsat x0, x2, x12 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.subsat x22, x0, x12 -# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction qc.subsat x22, x2, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.subsat x22, x2, x12 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.subusat x9, x14, 17 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.subusat x9, x14 -# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction qc.subusat x0, x14, x17 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.subusat x9, x0, x17 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.subusat x9, x14, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.subusat x9, x14, x17 -# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction qc.wrap x3, x30, 23 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.wrap x3, x30 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.wrap x0, x30, x23 -# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction qc.wrap x3, x30, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.wrap x3, x30, x23 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.wrapi x0, 12, 2047 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.wrapi x0, x12, 2047 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.wrapi x6, x0, 2047 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -153,48 +183,57 @@ qc.wrapi x6, x12, 2048 qc.wrapi x6, x12, 2047 -# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction qc.norm x3, 7 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.norm x3 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.norm x0, x7 -# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction qc.norm x3, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.norm x3, x7 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.normu x11, 17 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.normu x11 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.normu x0, x17 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.normu x11, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) qc.normu x11, x17 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.normeu x26, 31 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.normeu x26 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.normeu x0, x31 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.normeu x26, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension) diff --git a/llvm/test/MC/RISCV/xqciac-invalid.s b/llvm/test/MC/RISCV/xqciac-invalid.s index c595888ddee3e..3f2d8733b7032 100644 --- a/llvm/test/MC/RISCV/xqciac-invalid.s +++ b/llvm/test/MC/RISCV/xqciac-invalid.s @@ -4,7 +4,8 @@ # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciac < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.c.muliadd x5, x10, 4 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -17,7 +18,8 @@ qc.c.muliadd x10, x15, 32 qc.c.muliadd x10, x15, 20 -# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction qc.muliadd x0, x10, 1048577 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -30,7 +32,8 @@ qc.muliadd x10, x15, 8589934592 qc.muliadd x10, x15, 577 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.shladd 0, x10, 1048577 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/xqcicli-invalid.s b/llvm/test/MC/RISCV/xqcicli-invalid.s index 7ee92ec4cbc01..a2f5549a394f4 100644 --- a/llvm/test/MC/RISCV/xqcicli-invalid.s +++ b/llvm/test/MC/RISCV/xqcicli-invalid.s @@ -4,13 +4,16 @@ # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicli < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.lieq x0, x4, x6, 10 -# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction qc.lieq x2, x0, x6, 10 -# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction qc.lieq x2, x4, x0, 10 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -23,13 +26,16 @@ qc.lieq x2, x4, x6, 40 qc.lieq x2, x4, x6, 10 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.lige x0, x8, x20, 2 -# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction qc.lige x4, x0, x20, 2 -# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction qc.lige x4, x8, x0, 2 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -42,13 +48,16 @@ qc.lige x4, x8, x20, -18 qc.lige x4, x8, x20, 2 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.lilt x0, x9, x10, 3 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.lilt x19, x0, x10, 3 -# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction qc.lilt x19, x9, x0, 3 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -61,13 +70,16 @@ qc.lilt x19, x9, x10, 39 qc.lilt x19, x9, x10, 3 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.line x0, x14, x6, 10 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.line x18, x0, x6, 10 -# CHECK: :[[@LINE+1]]:19: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:19: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:19: error: invalid operand for instruction qc.line x18, x14, x0, 10 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -80,13 +92,16 @@ qc.line x18, x14, x6, 100 qc.line x18, x14, x6, 10 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.ligeu x0, x4, x6, 10 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.ligeu x2, x0, x6, 10 -# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction qc.ligeu x2, x4, x0, 10 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -99,13 +114,16 @@ qc.ligeu x2, x4, x6, 70 qc.ligeu x2, x4, x6, 10 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.liltu x0, x19, x12, 13 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.liltu x1, x0, x12, 13 -# CHECK: :[[@LINE+1]]:19: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:19: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:19: error: invalid operand for instruction qc.liltu x1, x19, x0, 13 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -118,10 +136,12 @@ qc.liltu x1, x19, x12, 73 qc.liltu x1, x19, x12, 13 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.lieqi x0, x1, 15, 12 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.lieqi x7, x0, 15, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -137,10 +157,12 @@ qc.lieqi x7, x1, 15, -22 qc.lieqi x7, x1, 15, 12 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.ligei x0, x11, -4, 9 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.ligei x17, x0, -4, 9 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -156,10 +178,12 @@ qc.ligei x17, x11, -4, 59 qc.ligei x17, x11, -4, 9 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.lilti x0, x11, -14, 2 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.lilti x9, x0, -14, 2 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -175,10 +199,12 @@ qc.lilti x9, x11, -14, 52 qc.lilti x9, x11, -14, 2 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.linei x0, x1, 10, 12 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.linei x5, x0, 10, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -194,10 +220,12 @@ qc.linei x5, x1, 10, 124 qc.linei x5, x1, 10, 12 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.ligeui x0, x12, 7, -12 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.ligeui x2, x0, 7, -12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -213,10 +241,12 @@ qc.ligeui x2, x12, 7, -17 qc.ligeui x2, x12, 7, -12 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.liltui x0, x25, 31, 12 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.liltui x3, x0, 31, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/xqcicm-invalid.s b/llvm/test/MC/RISCV/xqcicm-invalid.s index 8b37ed4edeb00..c1ee53fb21793 100644 --- a/llvm/test/MC/RISCV/xqcicm-invalid.s +++ b/llvm/test/MC/RISCV/xqcicm-invalid.s @@ -4,7 +4,8 @@ # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicm < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s -# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction qc.c.mveqz 9, x10 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -14,7 +15,8 @@ qc.c.mveqz x9 qc.c.mveqz x9, x10 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.mveq 9, x10, x11, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -24,7 +26,8 @@ qc.mveq x9 qc.mveq x9, x10, x11, x12 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.mvge 9, x10, x11, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -34,7 +37,8 @@ qc.mvge x9 qc.mvge x9, x10, x11, x12 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.mvgeu 9, x10, x11, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -44,7 +48,8 @@ qc.mvgeu x9 qc.mvgeu x9, x10, x11, x12 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.mvlt 9, x10, x11, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -54,7 +59,8 @@ qc.mvlt x9 qc.mvlt x9, x10, x11, x12 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.mvltu 9, x10, x11, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -64,7 +70,8 @@ qc.mvltu x9 qc.mvltu x9, x10, x11, x12 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.mvne 9, x10, x11, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -74,7 +81,8 @@ qc.mvne x9 qc.mvne x9, x10, x11, x12 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.mveqi 9, x10, 5, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -87,7 +95,8 @@ qc.mveqi x9, x10, 17, x12 qc.mveqi x9, x10, 5, x12 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.mvgei 9, x10, 5, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -100,7 +109,8 @@ qc.mvgei x9, x10, 17, x12 qc.mvgei x9, x10, 5, x12 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.mvlti 9, x10, 5, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -113,7 +123,8 @@ qc.mvlti x9, x10, 17, x12 qc.mvlti x9, x10, 5, x12 -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.mvnei 9, x10, 5, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -126,7 +137,8 @@ qc.mvnei x9, x10, 17, x12 qc.mvnei x9, x10, 5, x12 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.mvltui 9, x10, 5, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -139,7 +151,8 @@ qc.mvltui x9, x10, 37, x12 qc.mvltui x9, x10, 5, x12 -# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.mvgeui 9, x10, 5, x12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/xqcics-invalid.s b/llvm/test/MC/RISCV/xqcics-invalid.s index e7effdfd263b6..e3eda3fcdc193 100644 --- a/llvm/test/MC/RISCV/xqcics-invalid.s +++ b/llvm/test/MC/RISCV/xqcics-invalid.s @@ -4,7 +4,8 @@ # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcics < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.selecteqi 9, 15, x4, x3 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -17,7 +18,8 @@ qc.selecteqi x9, 16, x4, x3 qc.selecteqi x9, 15, x4, x3 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.selectieq 8, x4, x3, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -30,7 +32,8 @@ qc.selectieq x8, x4, x3, 17 qc.selectieq x8, x4, x3, 12 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.selectieqi 9, 11, x3, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -46,7 +49,8 @@ qc.selectieqi x9, 11, x3, 18 qc.selectieqi x9, 11, x3, 12 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.selectiieq 9, x3, 11, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -62,7 +66,8 @@ qc.selectiieq x9, x3, 11, 17 qc.selectiieq x9, x3, 11, 12 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.selectiine 8, x3, 10, 11 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -78,7 +83,8 @@ qc.selectiine x8, x3, 12, 18 qc.selectiine x8, x3, 10, 11 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.selectine 8, x3, x4, 11 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -91,7 +97,8 @@ qc.selectine x8, x3, x4, 16 qc.selectine x8, x3, x4, 11 -# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction qc.selectinei 8, 11, x3, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -107,7 +114,8 @@ qc.selectinei x8, 11, x3, 18 qc.selectinei x8, 11, x3, 12 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.selectnei 8, 11, x3, x5 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/xqcicsr-invalid.s b/llvm/test/MC/RISCV/xqcicsr-invalid.s index 6d3d62d4b4b41..b4119dbf88272 100644 --- a/llvm/test/MC/RISCV/xqcicsr-invalid.s +++ b/llvm/test/MC/RISCV/xqcicsr-invalid.s @@ -4,7 +4,8 @@ # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicsr < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s -# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction qc.csrrwr x10, x5, x0 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -14,7 +15,8 @@ qc.csrrwr x10, x5 qc.csrrwr x10, x5, x20 -# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.csrrwri x20, 31, x0 # CHECK-PLUS: :[[@LINE+1]]:17: error: immediate must be an integer in the range [0, 31] diff --git a/llvm/test/MC/RISCV/xqciint-invalid.s b/llvm/test/MC/RISCV/xqciint-invalid.s index e748109f41d82..34da463cb49c9 100644 --- a/llvm/test/MC/RISCV/xqciint-invalid.s +++ b/llvm/test/MC/RISCV/xqciint-invalid.s @@ -1,10 +1,11 @@ # Xqciint - Qualcomm uC Interrupts extension # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqciint < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciint < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s -# CHECK-IMM: :[[@LINE+1]]:12: error: immediate must be an integer in the range [0, 1023] +# CHECK-PLUS: :[[@LINE+2]]:12: error: immediate must be an integer in the range [0, 1023] +# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction qc.setinti 1025 # CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction @@ -13,11 +14,11 @@ qc.setinti 11, 12 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.setinti -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.setinti 10 -# CHECK-IMM: :[[@LINE+1]]:12: error: immediate must be an integer in the range [0, 1023] +# CHECK-PLUS: :[[@LINE+1]]:12: error: immediate must be an integer in the range [0, 1023] qc.clrinti 2000 # CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction @@ -26,80 +27,84 @@ qc.clrinti 22, x4 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.clrinti -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.clrinti 8 -# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction qc.c.clrint 22 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.c.clrint -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.clrint x8 # CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction qc.c.di 22 -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.di -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.c.dir 22 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.c.dir -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.dir x8 # CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction qc.c.ei 22 -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.ei -# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction qc.c.eir 22 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.c.eir -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.eir x8 # CHECK: :[[@LINE+1]]:19: error: invalid operand for instruction qc.c.mienter.nest 22 -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.mienter.nest # CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction qc.c.mienter 22 -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.mienter # CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction qc.c.mileaveret 22 -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.mileaveret -# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:13: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction qc.c.setint 22 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.c.setint -# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension) qc.c.setint x8 diff --git a/llvm/test/MC/RISCV/xqcilsm-invalid.s b/llvm/test/MC/RISCV/xqcilsm-invalid.s index c59260b5718d0..15d55021d64e4 100644 --- a/llvm/test/MC/RISCV/xqcilsm-invalid.s +++ b/llvm/test/MC/RISCV/xqcilsm-invalid.s @@ -7,7 +7,8 @@ # CHECK: :[[@LINE+1]]:20: error: expected register qc.swm x5, x20, 12(20) -# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction qc.swm x5, x0, 12(x3) # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -42,7 +43,8 @@ qc.swmi x10, 4, 20(x4) # CHECK: :[[@LINE+1]]:23: error: expected register qc.setwm x4, x30, 124(2) -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.setwm x4, x0, 124(x2) # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -80,7 +82,8 @@ qc.lwm x7, x1, 24(20) # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.lwm x7, x1, 24 -# CHECK: :[[@LINE+1]]:8: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:8: error: invalid operand for instruction qc.lwm x0, x1, 24(x20) # CHECK-PLUS: :[[@LINE+1]]:16: error: immediate must be a multiple of 4 bytes in the range [0, 124] @@ -96,7 +99,8 @@ qc.lwmi x13, 9, 4(23) # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.lwmi x13, 9, 4 -# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction qc.lwmi x0, 9, 4(x23) # CHECK-PLUS: :[[@LINE+1]]:14: error: immediate must be an integer in the range [1, 31] diff --git a/llvm/test/MC/RISCV/xqcisls-invalid.s b/llvm/test/MC/RISCV/xqcisls-invalid.s index 5e9e54812fee8..58a0f8ceaab35 100644 --- a/llvm/test/MC/RISCV/xqcisls-invalid.s +++ b/llvm/test/MC/RISCV/xqcisls-invalid.s @@ -4,13 +4,15 @@ # RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisls < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.lrb x5, x2, x0, 4 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.lrb x5, x2, x4 -# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 7] +# CHECK-PLUS: :[[@LINE+2]]:20: error: immediate must be an integer in the range [0, 7] +# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction qc.lrb x5, x2, x4, 12 # CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction @@ -20,13 +22,15 @@ qc.lrb x5, 2, x4, 4 qc.lrb x5, x2, x4, 4 -# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction qc.lrh x1, x12, x0, 2 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.lrh x1, x12, x6 -# CHECK-PLUS: :[[@LINE+1]]:21: error: immediate must be an integer in the range [0, 7] +# CHECK-PLUS: :[[@LINE+2]]:21: error: immediate must be an integer in the range [0, 7] +# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.lrh x1, x12, x6, 22 # CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction @@ -36,13 +40,15 @@ qc.lrh x1, 12, x6, 2 qc.lrh x1, x12, x6, 2 -# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction qc.lrw x15, x7, x0, 1 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.lrw x15, x7, x14 -# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7] +# CHECK-PLUS: :[[@LINE+2]]:22: error: immediate must be an integer in the range [0, 7] +# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction qc.lrw x15, x7, x14, 11 # CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction @@ -52,13 +58,15 @@ qc.lrw x15, 7, x14, 1 qc.lrw x15, x7, x14, 1 -# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction qc.lrbu x9, x11, x0, 7 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.lrbu x9, x11, x4 -# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7] +# CHECK-PLUS: :[[@LINE+2]]:22: error: immediate must be an integer in the range [0, 7] +# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction qc.lrbu x9, x11, x4, 37 # CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction @@ -68,13 +76,15 @@ qc.lrbu x9, 11, x4, 7 qc.lrbu x9, x11, x4, 7 -# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction qc.lrhu x16, x6, x0, 4 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.lrhu x16, x6, x10 -# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [0, 7] +# CHECK-PLUS: :[[@LINE+2]]:23: error: immediate must be an integer in the range [0, 7] +# CHECK-MINUS: :[[@LINE+1]]:23: error: invalid operand for instruction qc.lrhu x16, x6, x10, 44 # CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction @@ -84,13 +94,15 @@ qc.lrhu x16, 6, x10, 4 qc.lrhu x16, x6, x10, 4 -# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction qc.srb x0, x2, x0, 3 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.srb x0, x2, x8 -# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 7] +# CHECK-PLUS: :[[@LINE+2]]:20: error: immediate must be an integer in the range [0, 7] +# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction qc.srb x0, x2, x8, 93 # CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction @@ -100,13 +112,15 @@ qc.srb x0, 2, x8, 3 qc.srb x0, x2, x8, 3 -# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction qc.srh x13, x0, x0, 6 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.srh x13, x0, x20 -# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7] +# CHECK-PLUS: :[[@LINE+2]]:22: error: immediate must be an integer in the range [0, 7] +# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction qc.srh x13, x0, x20, 76 # CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction @@ -116,13 +130,15 @@ qc.srh x13, 0, x20, 6 qc.srh x13, x0, x20, 6 -# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0) +# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction qc.srw x17, x18, x0, 0 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction qc.srw x17, x18, x19 -# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [0, 7] +# CHECK-PLUS: :[[@LINE+2]]:23: error: immediate must be an integer in the range [0, 7] +# CHECK-MINUS: :[[@LINE+1]]:23: error: invalid operand for instruction qc.srw x17, x18, x19, 10 # CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/zicfiss-invalid.s b/llvm/test/MC/RISCV/zicfiss-invalid.s index a5ab9240f3fad..f978d8c2c5ce8 100644 --- a/llvm/test/MC/RISCV/zicfiss-invalid.s +++ b/llvm/test/MC/RISCV/zicfiss-invalid.s @@ -15,5 +15,5 @@ c.sspopchk ra # CHECK-ERR: error: register must be ra or t0 (x1 or x5) sspush a0 -# CHECK-ERR: error: invalid operand for instruction +# CHECK-ERR: error: register must be a GPR excluding zero (x0) ssrdp zero