diff --git a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
new file mode 100644
index 0000000000000..ab960a7084528
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
@@ -0,0 +1,42 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills %s -o /dev/null 2>&1 | FileCheck -check-prefix=VERIFIER %s
+
+# FIXME : Currently, MRI's liveIn check for registers does not take the corresponding live-in's sub-registers into account. As a result
+# in SILowerSGPRSpills, the SubReg spill gets marked KILLED even though its SuperReg is in the function Live-ins. This causes machine
+# verifier to now fail at direct usage of that SubReg, which intially should not be any problem before adding spill.
+
+# VERIFIER: After SI lower SGPR spill instructions
+
+# VERIFIER: *** Bad machine code: Using an undefined physical register ***
+# VERIFIER: - instruction: S_NOP 0, implicit $sgpr50
+# VERIFIER-NEXT: - operand 1:   implicit $sgpr50
+
+# VERIFIER: *** Bad machine code: Using an undefined physical register ***
+# VERIFIER: - instruction: S_NOP 0, implicit $sgpr52
+# VERIFIER-NEXT: - operand 1:   implicit $sgpr52
+
+# VERIFIER: *** Bad machine code: Using an undefined physical register ***
+# VERIFIER: - instruction: S_NOP 0, implicit $sgpr55
+# VERIFIER-NEXT: - operand 1:   implicit $sgpr55
+
+# VERIFIER: LLVM ERROR: Found 3 machine code errors. 
+---
+name: spill_partial_live_csr_sgpr_test
+tracksRegLiveness: true
+liveins:
+  - { reg: '$sgpr50_sgpr51' }
+  - { reg: '$sgpr52_sgpr53' }
+  - { reg: '$sgpr54_sgpr55' }
+body:             |
+  bb.0:
+    liveins: $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
+
+    S_NOP 0, implicit $sgpr50
+    $sgpr50 = S_MOV_B32 0
+    S_NOP 0, implicit $sgpr52
+    $sgpr52_sgpr53 = S_MOV_B64 0
+    S_NOP 0, implicit $sgpr55
+    $sgpr54_sgpr55 = S_MOV_B64 0
+    $sgpr56 = S_MOV_B32 0
+...
+