diff --git a/llvm/lib/Target/ARM/ARMParallelDSP.cpp b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
index a2b2cf1323cae..4e92720de4755 100644
--- a/llvm/lib/Target/ARM/ARMParallelDSP.cpp
+++ b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
@@ -300,7 +300,8 @@ bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1,
   if (!Ld0 || !Ld1)
     return false;
 
-  if (!LoadPairs.count(Ld0) || LoadPairs[Ld0] != Ld1)
+  auto It = LoadPairs.find(Ld0);
+  if (It == LoadPairs.end() || It->second != Ld1)
     return false;
 
   LLVM_DEBUG(dbgs() << "Loads are sequential and valid:\n";
@@ -382,8 +383,8 @@ bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) {
     LoadInst *Dominator = BaseFirst ? Base : Offset;
     LoadInst *Dominated = BaseFirst ? Offset : Base;
 
-    if (RAWDeps.count(Dominated)) {
-      InstSet &WritesBefore = RAWDeps[Dominated];
+    if (auto It = RAWDeps.find(Dominated); It != RAWDeps.end()) {
+      InstSet &WritesBefore = It->second;
 
       for (auto *Before : WritesBefore) {
         // We can't move the second load backward, past a write, to merge