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@llvmbot llvmbot commented Feb 15, 2025

Backport 256145b

Requested by: @topperc

@llvmbot llvmbot added this to the LLVM 20.X Release milestone Feb 15, 2025
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llvmbot commented Feb 15, 2025

@topperc What do you think about merging this PR to the release branch?

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llvmbot commented Feb 15, 2025

@llvm/pr-subscribers-backend-powerpc

Author: None (llvmbot)

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Backport 256145b

Requested by: @topperc


Full diff: https://github.com/llvm/llvm-project/pull/127350.diff

2 Files Affected:

  • (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+2-2)
  • (added) llvm/test/CodeGen/PowerPC/pr127298.ll (+13)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4ca328bd9a9ba..21ff6f050817a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -19050,8 +19050,8 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
         int32_t Addr = (int32_t)CNImm;
         // Otherwise, break this down into LIS + Disp.
         Disp = DAG.getSignedTargetConstant((int16_t)Addr, DL, MVT::i32);
-        Base =
-            DAG.getTargetConstant((Addr - (int16_t)Addr) >> 16, DL, MVT::i32);
+        Base = DAG.getSignedTargetConstant((Addr - (int16_t)Addr) >> 16, DL,
+                                           MVT::i32);
         uint32_t LIS = CNType == MVT::i32 ? PPC::LIS : PPC::LIS8;
         Base = SDValue(DAG.getMachineNode(LIS, DL, CNType, Base), 0);
         break;
diff --git a/llvm/test/CodeGen/PowerPC/pr127298.ll b/llvm/test/CodeGen/PowerPC/pr127298.ll
new file mode 100644
index 0000000000000..f7560216ef7d8
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr127298.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=powerpc | FileCheck %s
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %Entry
+; CHECK-NEXT:    lis 3, -8530
+; CHECK-NEXT:    lbz 3, -16657(3)
+; CHECK-NEXT:    blr
+Entry:
+  %0 = load volatile i8, ptr inttoptr (i32 -559038737 to ptr), align 1
+  ret void
+}

@tstellar tstellar merged commit 9429165 into llvm:release/20.x Feb 16, 2025
7 of 11 checks passed
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@topperc (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR.

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4 participants