[WIP][RISC-V] prototyping intrinsic support for Zvbc32e and Zvkgs

clang/include/clang/Basic/riscv_vector.td

@@ -2787,6 +2787,17 @@ multiclass RVVSignedWidenBinBuiltinSetVwsll
                          [["vv", "Uw", "UwUvUv"],
                           ["vx", "Uw", "UwUvz"]]>;
 
+// intrinsic class for an instruction with integer operand up
+// up to 32-bit wide
+multiclass RVVIntMax32BinBuiltinSet
+    : RVVOutOp1BuiltinSet<NAME, "csi",
+                          [["vv", "v", "vvv"],
+                           ["vx", "v", "vve"]]>,
+      RVVOutOp1BuiltinSet<NAME, "csi",
+                          [["vv", "Uv", "UvUvUv"],
+                           ["vx", "Uv", "UvUvUe"]]>;
+
+
 let UnMaskedPolicyScheme = HasPassthruOperand in {
   // zvkb
   let RequiredFeatures = ["Zvkb"] in {
@@ -2813,6 +2824,12 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
     defm vclmul  : RVVInt64BinBuiltinSet;
     defm vclmulh : RVVInt64BinBuiltinSet;
   }
+
+  // zvbc32e
+  let RequiredFeatures = ["Zvbc32e", "Experimental"] in {
+    defm vclmul  : RVVIntMax32BinBuiltinSet  ;
+    defm vclmulh : RVVIntMax32BinBuiltinSet;
+  }
 }
 
 let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {

clang/include/clang/Support/RISCVVIntrinsicUtils.h

@@ -503,6 +503,8 @@ enum RVVRequire {
   RVV_REQ_Zvfbfwma,
   RVV_REQ_Zvfbfmin,
   RVV_REQ_Zvfh,
+  RVV_REQ_Zvbc32e,
+  RVV_REQ_Zvkgs,
   RVV_REQ_Experimental,
   RVV_REQ_NUM,
 };

clang/lib/Sema/SemaRISCV.cpp

@@ -225,6 +225,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
       {"zvfbfwma", RVV_REQ_Zvfbfwma},
       {"zvfbfmin", RVV_REQ_Zvfbfmin},
       {"zvfh", RVV_REQ_Zvfh},
+      {"zvbc32e", RVV_REQ_Zvbc32e},
+      {"zvkgs", RVV_REQ_Zvkgs},
       {"experimental", RVV_REQ_Experimental}};
 
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics

clang/utils/TableGen/RISCVVEmitter.cpp

@@ -792,6 +792,8 @@ void RVVEmitter::createRVVIntrinsics(
               .Case("Zvfbfwma", RVV_REQ_Zvfbfwma)
               .Case("Zvfbfmin", RVV_REQ_Zvfbfmin)
               .Case("Zvfh", RVV_REQ_Zvfh)
+              .Case("Zvbc32e", RVV_REQ_Zvbc32e)
+              .Case("Zvkgs", RVV_REQ_Zvkgs)
               .Case("Experimental", RVV_REQ_Experimental);
       SR.RequiredExtensions[RequireExt / 32] |= 1U << (RequireExt % 32);
     }

llvm/docs/RISCVUsage.rst

@@ -222,6 +222,7 @@ on support follow.
      ``Ztso``          Supported
      ``Zvbb``          Supported
      ``Zvbc``          Supported (`See note <#riscv-vector-crypto-note>`__)
+     ``Zvbc32e``       Supported (`See note <#riscv-vector-crypto-note>`__)
      ``Zve32x``        (`Partially <#riscv-vlen-32-note>`__) Supported
      ``Zve32f``        (`Partially <#riscv-vlen-32-note>`__) Supported
      ``Zve64x``        Supported
@@ -233,6 +234,7 @@ on support follow.
      ``Zvfhmin``       Supported
      ``Zvkb``          Supported
      ``Zvkg``          Supported (`See note <#riscv-vector-crypto-note>`__)
+     ``Zvkgs``         Supported (`See note <#riscv-vector-crypto-note>`__)
      ``Zvkn``          Supported (`See note <#riscv-vector-crypto-note>`__)
      ``Zvknc``         Supported (`See note <#riscv-vector-crypto-note>`__)
      ``Zvkned``        Supported (`See note <#riscv-vector-crypto-note>`__)

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -327,6 +327,16 @@ let TargetPrefix = "riscv" in {
     let VLOperand = 2;
   }
 
+  // For destination vector type is the same as the source vector type
+  // Input: (passthru, vector_in, vector_in/scalar_in, vl, policy)
+  class RISCVBinaryAASUnMaskedZvk
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty,
+                     llvm_anyint_ty, LLVMMatchType<2>],
+                    [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
+    let VLOperand = 3;
+  }
+
   multiclass RISCVUnaryAAUnMaskedZvk<bit HasVV = 1, bit HasVS = 1> {
     if HasVV then
       def "int_riscv_" # NAME # "_vv" : RISCVUnaryAAUnMaskedZvk<IsVS=0>;
@@ -1847,14 +1857,18 @@ let TargetPrefix = "riscv" in {
   defm vcpopv            : RISCVUnaryAA;
   defm vwsll             : RISCVBinaryABX;
 
-  // Zvbc
+  // Zvbc / Zvbc32e
   defm vclmul            : RISCVBinaryAAX;
   defm vclmulh           : RISCVBinaryAAX;
 
   // Zvkg
   def int_riscv_vghsh    : RISCVBinaryAAXUnMaskedZvk;
   def int_riscv_vgmul_vv : RISCVUnaryAAUnMaskedZvk<IsVS=0>;
 
+  // Zvkgs
+  def int_riscv_vghsh_vs : RISCVBinaryAASUnMaskedZvk;
+  def int_riscv_vgmul_vs : RISCVUnaryAAUnMaskedZvk<IsVS=1>;
+
   // Zvkned
   defm vaesdf            : RISCVUnaryAAUnMaskedZvk;
   defm vaesdm            : RISCVUnaryAAUnMaskedZvk;

llvm/lib/TargetParser/RISCVISAInfo.cpp

@@ -1075,7 +1075,8 @@ constexpr static RISCVExtBit RISCVBitPositions[] = {
     {"zimop", 1, 1},      {"zca", 1, 2},
     {"zcb", 1, 3},        {"zcd", 1, 4},
     {"zcf", 1, 5},        {"zcmop", 1, 6},
-    {"zawrs", 1, 7}};
+    {"zawrs", 1, 7},      {"zvbc32e", 1, 8},
+    {"zvkgs", 1, 9}};
 
 std::pair<int, int> RISCVISAInfo::getRISCVFeaturesBitsInfo(StringRef Ext) {
   // Note that this code currently accepts mixed case extension names, but