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[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. #128473

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Feb 24, 2025
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[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. #128473

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2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Expand Up @@ -1035,7 +1035,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// marked renamable.
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const DebugLoc &DL,
MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
Register DestReg, Register SrcReg, bool KillSrc,
bool RenamableDest = false,
bool RenamableSrc = false) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
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8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Expand Up @@ -4988,8 +4988,8 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,

void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
if (AArch64::GPR32spRegClass.contains(DestReg) &&
Expand Down Expand Up @@ -5068,8 +5068,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
auto ToPPR = [](MCRegister R) -> MCRegister {
return (R - AArch64::PN0) + AArch64::P0;
};
MCRegister PPRSrcReg = SrcIsPNR ? ToPPR(SrcReg) : SrcReg;
MCRegister PPRDestReg = DestIsPNR ? ToPPR(DestReg) : DestReg;
MCRegister PPRSrcReg = SrcIsPNR ? ToPPR(SrcReg) : SrcReg.asMCReg();
MCRegister PPRDestReg = DestIsPNR ? ToPPR(DestReg) : DestReg.asMCReg();

if (PPRSrcReg != PPRDestReg) {
auto NewMI = BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), PPRDestReg)
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.h
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Expand Up @@ -343,7 +343,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool KillSrc, unsigned Opcode, unsigned ZeroReg,
llvm::ArrayRef<unsigned> Indices) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
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Expand Up @@ -37,8 +37,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {

void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
unsigned VectorComponents = 0;
if ((R600::R600_Reg128RegClass.contains(DestReg) ||
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/R600InstrInfo.h
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Expand Up @@ -73,7 +73,7 @@ class R600InstrInfo final : public R600GenInstrInfo {
}

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -801,9 +801,9 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,

void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc, bool RenamableDest,
bool RenamableSrc) const {
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
unsigned Size = RI.getRegSizeInBits(*RC);
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
Expand All @@ -816,7 +816,7 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (((Size == 16) != (SrcSize == 16))) {
// Non-VGPR Src and Dst will later be expanded back to 32 bits.
assert(ST.hasTrue16BitInsts());
MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
Register &RegToFix = (Size == 32) ? DestReg : SrcReg;
MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
RegToFix = SubReg;

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -263,7 +263,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
int64_t Offset1, unsigned NumLoads) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARC/ARCInstrInfo.cpp
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Expand Up @@ -280,8 +280,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,

void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
assert(ARC::GPR32RegClass.contains(SrcReg) &&
"Only GPR32 src copy supported.");
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARC/ARCInstrInfo.h
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Expand Up @@ -64,7 +64,7 @@ class ARCInstrInfo : public ARCGenInstrInfo {
int *BytesRemoved = nullptr) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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Expand Up @@ -889,8 +889,8 @@ void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,

void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
bool GPRDest = ARM::GPRRegClass.contains(DestReg);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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Expand Up @@ -208,7 +208,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
const ARMSubtarget &Subtarget) const;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
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Expand Up @@ -41,8 +41,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {

void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
// Need to check the arch.
MachineFunction &MF = *MBB.getParent();
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/Thumb1InstrInfo.h
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Expand Up @@ -38,7 +38,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
void storeRegToStackSlot(
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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
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Expand Up @@ -149,8 +149,8 @@ Thumb2InstrInfo::optimizeSelect(MachineInstr &MI,

void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
// Handle SPR, DPR, and QPR copies.
if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/Thumb2InstrInfo.h
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Expand Up @@ -38,7 +38,7 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
MachineBasicBlock::iterator MBBI) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AVR/AVRInstrInfo.cpp
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Expand Up @@ -35,8 +35,8 @@ AVRInstrInfo::AVRInstrInfo(AVRSubtarget &STI)

void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
unsigned Opc;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AVR/AVRInstrInfo.h
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Expand Up @@ -74,7 +74,7 @@ class AVRInstrInfo : public AVRGenInstrInfo {
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
void storeRegToStackSlot(
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/BPF/BPFInstrInfo.cpp
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Expand Up @@ -30,8 +30,8 @@ BPFInstrInfo::BPFInstrInfo()

void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
if (BPF::GPRRegClass.contains(DestReg, SrcReg))
BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
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2 changes: 1 addition & 1 deletion llvm/lib/Target/BPF/BPFInstrInfo.h
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Expand Up @@ -30,7 +30,7 @@ class BPFInstrInfo : public BPFGenInstrInfo {
const BPFRegisterInfo &getRegisterInfo() const { return RI; }

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
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Expand Up @@ -476,8 +476,8 @@ void CSKYInstrInfo::loadRegFromStackSlot(

void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
if (CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::CARRYRegClass.contains(DestReg)) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/CSKY/CSKYInstrInfo.h
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Expand Up @@ -53,7 +53,7 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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Expand Up @@ -858,8 +858,8 @@ static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {

void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonInstrInfo.h
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Expand Up @@ -173,7 +173,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// careful implementation when multiple copy instructions are required for
/// large registers. See for example the ARM target.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
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Expand Up @@ -32,8 +32,8 @@ LanaiInstrInfo::LanaiInstrInfo()
void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Position,
const DebugLoc &DL,
MCRegister DestinationRegister,
MCRegister SourceRegister, bool KillSource,
Register DestinationRegister,
Register SourceRegister, bool KillSource,
bool RenamableDest, bool RenamableSrc) const {
if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
llvm_unreachable("Impossible reg-to-reg copy");
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Lanai/LanaiInstrInfo.h
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Expand Up @@ -48,8 +48,8 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
int &FrameIndex) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
const DebugLoc &DL, MCRegister DestinationRegister,
MCRegister SourceRegister, bool KillSource,
const DebugLoc &DL, Register DestinationRegister,
Register SourceRegister, bool KillSource,
bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
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Expand Up @@ -39,8 +39,8 @@ MCInst LoongArchInstrInfo::getNop() const {

void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DstReg,
Register SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
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2 changes: 1 addition & 1 deletion llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
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Expand Up @@ -30,7 +30,7 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {
MCInst getNop() const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
const DebugLoc &DL, Register DstReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/M68k/M68kInstrInfo.cpp
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Expand Up @@ -705,8 +705,8 @@ bool M68kInstrInfo::isPCRelRegisterOperandLegal(

void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DstReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DstReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
unsigned Opc = 0;

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2 changes: 1 addition & 1 deletion llvm/lib/Target/M68k/M68kInstrInfo.h
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Expand Up @@ -270,7 +270,7 @@ class M68kInstrInfo : public M68kGenInstrInfo {
int *BytesAdded = nullptr) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
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Expand Up @@ -83,8 +83,8 @@ void MSP430InstrInfo::loadRegFromStackSlot(

void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
unsigned Opc;
if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
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2 changes: 1 addition & 1 deletion llvm/lib/Target/MSP430/MSP430InstrInfo.h
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Expand Up @@ -36,7 +36,7 @@ class MSP430InstrInfo : public MSP430GenInstrInfo {
const MSP430RegisterInfo &getRegisterInfo() const { return RI; }

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

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4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/Mips16InstrInfo.cpp
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Expand Up @@ -65,8 +65,8 @@ Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,

void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
const DebugLoc &DL, Register DestReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
unsigned Opc = 0;

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2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/Mips16InstrInfo.h
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Expand Up @@ -49,7 +49,7 @@ class Mips16InstrInfo : public MipsInstrInfo {
int &FrameIndex) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
const DebugLoc &DL, Register DestReg, Register SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

Expand Down
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