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[MachineScheduler][AMDGPU] Allow scheduling of single-MI regions #128739

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Merged
merged 5 commits into from
Feb 27, 2025
Merged

[MachineScheduler][AMDGPU] Allow scheduling of single-MI regions #128739

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aeed954
Allow scheduling of regions with single MI
lucas-rami Feb 25, 2025
1d43cbf
Revert spurious formatting change
lucas-rami Feb 25, 2025
252bce6
Fix comment typo
lucas-rami Feb 25, 2025
db36039
Remove flag; this is now the default scheduler behavior
lucas-rami Feb 26, 2025
0f41fe8
Update comment in machine scheduler
lucas-rami Feb 27, 2025
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8 changes: 8 additions & 0 deletions llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
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Expand Up @@ -124,6 +124,9 @@ namespace llvm {
/// rescheduling).
bool RemoveKillFlags;

/// True if regions with a single MI should be scheduled.
bool ScheduleSingleMIRegions = false;
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@arsenm arsenm Feb 26, 2025

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Over-configuration? Can you just unconditionally do this?

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@lucas-rami lucas-rami Feb 26, 2025

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I removed the flag and made this the generic scheduler behavior. The only unit test that breaks in a way I cannot really understand is misched-branch-targets.mir. I "fixed" it anyway, but not sure if the change break something here.


/// The standard DAG builder does not normally include terminators as DAG
/// nodes because it does not create the necessary dependencies to prevent
/// reordering. A specialized scheduler can override
Expand Down Expand Up @@ -288,6 +291,11 @@ namespace llvm {
return Topo.IsReachable(SU, TargetSU);
}

/// Whether regions with a single MI should be scheduled.
bool shouldScheduleSingleMIRegions() const {
return ScheduleSingleMIRegions;
}

/// Returns an iterator to the top of the current scheduling region.
MachineBasicBlock::iterator begin() const { return RegionBegin; }

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3 changes: 2 additions & 1 deletion llvm/lib/CodeGen/MachineScheduler.cpp
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Expand Up @@ -770,6 +770,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,

MBBRegionsVector MBBRegions;
getSchedRegions(&*MBB, MBBRegions, Scheduler.doMBBSchedRegionsTopDown());
bool ScheduleSingleMI = Scheduler.shouldScheduleSingleMIRegions();
for (const SchedRegion &R : MBBRegions) {
MachineBasicBlock::iterator I = R.RegionBegin;
MachineBasicBlock::iterator RegionEnd = R.RegionEnd;
Expand All @@ -780,7 +781,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
Scheduler.enterRegion(&*MBB, I, RegionEnd, NumRegionInstrs);

// Skip empty scheduling regions (0 or 1 schedulable instructions).
if (I == RegionEnd || I == std::prev(RegionEnd)) {
if (I == RegionEnd || (!ScheduleSingleMI && I == std::prev(RegionEnd))) {
// Close the current region. Bundle the terminator if needed.
// This invalidates 'RegionEnd' and 'I'.
Scheduler.exitRegion();
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5 changes: 4 additions & 1 deletion llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
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Expand Up @@ -759,7 +759,10 @@ GCNScheduleDAGMILive::GCNScheduleDAGMILive(
MFI(*MF.getInfo<SIMachineFunctionInfo>()),
StartingOccupancy(MFI.getOccupancy()), MinOccupancy(StartingOccupancy),
RegionLiveOuts(this, /*IsLiveOut=*/true) {

// We want regions with a single MI to be scheduled so that we can reason on
// them correctly during scheduling stages that move MIs between regions (e.g.
// rematerialization).
ScheduleSingleMIRegions = true;
LLVM_DEBUG(dbgs() << "Starting occupancy is " << StartingOccupancy << ".\n");
if (RelaxedOcc) {
MinOccupancy = std::min(MFI.getMinAllowedOccupancy(), StartingOccupancy);
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2 changes: 2 additions & 0 deletions llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
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Expand Up @@ -2,6 +2,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
# REQUIRES: asserts

# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: test_get_liveins:%bb.0
# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: test_get_liveins:%bb.1
# CHECK: Region live-in pressure: VGPRs: 1 AGPRs: 0, SGPRs: 0, LVGPR WT: 0, LSGPR WT: 0
Expand Down