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[AMDGPU] Skip handling of non-byte types in promote alloca. #128769

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[AMDGPU] Skip handling of non-byte types in promote alloca. #128769

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11 changes: 9 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -759,6 +759,14 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToVector(AllocaInst &Alloca) {
return false;
}

Type *VecEltTy = VectorTy->getElementType();
constexpr unsigned SIZE_OF_BYTE = 8;
unsigned ElementSizeInBits = DL->getTypeSizeInBits(VecEltTy);
// FIXME: The non-byte type like i1 can be packed and be supported, but
// currently we do not handle them.
if (ElementSizeInBits % SIZE_OF_BYTE != 0)
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@arsenm arsenm Feb 26, 2025

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Best to replicate typeSizeEqualsStoreSize

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@sgundapa sgundapa Feb 27, 2025

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Thanks. Will do

return false;

std::map<GetElementPtrInst *, WeakTrackingVH> GEPVectorIdx;
SmallVector<Instruction *> WorkList;
SmallVector<Instruction *> UsersToRemove;
Expand All @@ -776,8 +784,7 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToVector(AllocaInst &Alloca) {

LLVM_DEBUG(dbgs() << " Attempting promotion to: " << *VectorTy << "\n");

Type *VecEltTy = VectorTy->getElementType();
unsigned ElementSize = DL->getTypeSizeInBits(VecEltTy) / 8;
unsigned ElementSize = ElementSizeInBits / SIZE_OF_BYTE;
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@shiltian shiltian Feb 25, 2025

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IIUC SIZE_OF_BYTE is defined by the whatever compiler compiles LLVM instead of for AMDGPU.

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@sgundapa sgundapa Feb 25, 2025

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You mean , to use some thing like this to derive the value from data layout "DL.getTypeSizeInBits(Type::getInt8Ty(M->getContext()))".

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@sgundapa sgundapa Feb 25, 2025

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I have defined it to be "constexpr unsigned SIZE_OF_BYTE = 8" in line 763. Probably pick a different name ?

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@shiltian shiltian Feb 25, 2025 •
edited
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Oh, I missed that part. Hardcoding 8 is probably fine for now and in the any near future, but the proper approach is definitely to query DL.

for (auto *U : Uses) {
Instruction *Inst = cast<Instruction>(U->getUser());

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21 changes: 21 additions & 0 deletions llvm/test/CodeGen/AMDGPU/promote-alloca-skip-non-byte-type.ll
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@@ -0,0 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s

; Verify that we do not crash and not promote non-byte alloca types.
define <8 x i1> @non_byte_alloca_type() {
; CHECK-LABEL: define <8 x i1> @non_byte_alloca_type() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[C:%.*]] = icmp ugt <16 x i1> zeroinitializer, zeroinitializer
; CHECK-NEXT: [[RP:%.*]] = alloca <8 x i1>, align 1
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i1>, ptr [[RP]], align 1
; CHECK-NEXT: store <16 x i1> [[C]], ptr [[RP]], align 2
; CHECK-NEXT: ret <8 x i1> [[TMP0]]
;
entry:
%C = icmp ugt <16 x i1> zeroinitializer, zeroinitializer
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@arsenm arsenm Feb 26, 2025

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Use something that can't fold away

%RP = alloca <8 x i1>, align 1
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@arsenm arsenm Feb 26, 2025

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Use the correct alloca address space. Also this issue isn't about the UB under-alignment, so correct that

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@sgundapa sgundapa Feb 27, 2025

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Thats correct. Here is an example that might trigger an UB

@g = global <8 x float> <float 4.200000e+01, float 4.200000e+01, float 4.200000e+01, float 4.200000e+01, float 4.200000e+01, float 4.200000e+01, float 4.200000e+01, float 4.200000e+01>

define <8 x i1> @f(float %0, i32 %1, i16 %2) {
BB:
%LGV = load <8 x float>, ptr @g, align 32
%RP = alloca <8 x i1>, align 1
%L = load <8 x float>, ptr %RP, align 32
%C = fcmp olt <8 x float> %L, %LGV
ret <8 x i1> %C
}

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@sgundapa sgundapa Feb 27, 2025

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Also, if you do not specify the addrspace , wouldn't it default to generic addrsapce which is "0"

%0 = load <8 x i1>, ptr %RP, align 1
store <16 x i1> %C, ptr %RP, align 2
ret <8 x i1> %0
}

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@arsenm arsenm Feb 26, 2025

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Can you add some tests for the scalar case? Only the subvector extract was a problem?

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@sgundapa sgundapa Feb 27, 2025

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The assertion trigered here is due to subvector being <2 x i1> and the access type being <16 x i1>
The access size for < 16 x i1> is 2 and the computation to derive the subvector relies on this access size and ended with a <2xi1> that triggered the assert due to mismatch in storage size.

assert(DL.getTypeStoreSize(SubVecTy) == DL.getTypeStoreSize(AccessTy));

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@sgundapa sgundapa Feb 27, 2025

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Yes, the assertions I am seeing are all being trigerred while handling subvectors for loads and stores.

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