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[LLVM][SVE] Add isel for bfloat based (de)interleave operations. #128875

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Merged
paulwalker-arm merged 2 commits into from
Feb 27, 2025
Merged

[LLVM][SVE] Add isel for bfloat based (de)interleave operations. #128875

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4fba5d3
[LLVM][SVE] Add isel for bfloat based (de)interleave operations.
paulwalker-arm Feb 26, 2025
b83d3f3
Fix whitespace formating within unit tests.
paulwalker-arm Feb 26, 2025
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2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1702,6 +1702,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::MLOAD, VT, Custom);
setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom);
setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom);
setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);

if (Subtarget->hasSVEB16B16()) {
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2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -3079,6 +3079,8 @@ multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm,
def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;

def : SVE_2_Op_Pat<nxv8bf16, op, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME # _H)>;
def : SVE_2_Op_Pat<nxv4bf16, op, nxv4bf16, nxv4bf16, !cast<Instruction>(NAME # _S)>;
def : SVE_2_Op_Pat<nxv2bf16, op, nxv2bf16, nxv2bf16, !cast<Instruction>(NAME # _D)>;
}

//===----------------------------------------------------------------------===//
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35 changes: 35 additions & 0 deletions llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
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Expand Up @@ -70,6 +70,41 @@ define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f
ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
}

define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv4bf16(<vscale x 4 x bfloat> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z1.s, z0.s, z0.s
; CHECK-NEXT: uzp2 z2.s, z0.s, z0.s
; CHECK-NEXT: uunpklo z0.d, z1.s
; CHECK-NEXT: uunpklo z1.d, z2.s
; CHECK-NEXT: ret
%retval = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave2.nxv4bf16(<vscale x 4 x bfloat> %vec)
ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval
}

define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv8bf16(<vscale x 8 x bfloat> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z1.h, z0.h, z0.h
; CHECK-NEXT: uzp2 z2.h, z0.h, z0.h
; CHECK-NEXT: uunpklo z0.s, z1.h
; CHECK-NEXT: uunpklo z1.s, z2.h
; CHECK-NEXT: ret
%retval = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave2.nxv8bf16(<vscale x 8 x bfloat> %vec)
ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval
}

define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv16bf16(<vscale x 16 x bfloat> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z2.h, z0.h, z1.h
; CHECK-NEXT: uzp2 z1.h, z0.h, z1.h
; CHECK-NEXT: mov z0.d, z2.d
; CHECK-NEXT: ret
%retval = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave2.nxv16bf16(<vscale x 16 x bfloat> %vec)
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval
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@david-arm david-arm Feb 26, 2025

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nit: There seems to be excess whitespace in %retval and similarly for the other tests in both files. Perhaps remove some whitespace before landing?

}

; Integers

define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv32i8(<vscale x 32 x i8> %vec) {
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33 changes: 33 additions & 0 deletions llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
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Expand Up @@ -67,6 +67,39 @@ define <vscale x 4 x double> @interleave2_nxv4f64(<vscale x 2 x double> %vec0, <
ret <vscale x 4 x double> %retval
}

define <vscale x 4 x bfloat> @interleave2_nxv4bf16(<vscale x 2 x bfloat> %vec0, <vscale x 2 x bfloat> %vec1) {
; CHECK-LABEL: interleave2_nxv4bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: zip2 z2.d, z0.d, z1.d
; CHECK-NEXT: zip1 z0.d, z0.d, z1.d
; CHECK-NEXT: uzp1 z0.s, z0.s, z2.s
; CHECK-NEXT: ret
%retval = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %vec0, <vscale x 2 x bfloat> %vec1)
ret <vscale x 4 x bfloat> %retval
}

define <vscale x 8 x bfloat> @interleave2_nxv8bf16(<vscale x 4 x bfloat> %vec0, <vscale x 4 x bfloat> %vec1) {
; CHECK-LABEL: interleave2_nxv8bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: zip2 z2.s, z0.s, z1.s
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT: ret
%retval = call <vscale x 8 x bfloat> @llvm.vector.interleave2.nxv8bf16(<vscale x 4 x bfloat> %vec0, <vscale x 4 x bfloat> %vec1)
ret <vscale x 8 x bfloat> %retval
}

define <vscale x 16 x bfloat> @interleave2_nxv16bf16(<vscale x 8 x bfloat> %vec0, <vscale x 8 x bfloat> %vec1) {
; CHECK-LABEL: interleave2_nxv16bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: zip1 z2.h, z0.h, z1.h
; CHECK-NEXT: zip2 z1.h, z0.h, z1.h
; CHECK-NEXT: mov z0.d, z2.d
; CHECK-NEXT: ret
%retval = call <vscale x 16 x bfloat> @llvm.vector.interleave2.nxv16bf16(<vscale x 8 x bfloat> %vec0, <vscale x 8 x bfloat> %vec1)
ret <vscale x 16 x bfloat> %retval
}

; Integers

define <vscale x 32 x i8> @interleave2_nxv32i8(<vscale x 16 x i8> %vec0, <vscale x 16 x i8> %vec1) {
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