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[AMDGPU][True16][CodeGen] gisel true16 for ICMP #128913

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Merged
merged 2 commits into from
Mar 13, 2025
Merged

[AMDGPU][True16][CodeGen] gisel true16 for ICMP #128913

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9fea04e
gisel update for icmp
broxigarchen Feb 28, 2025
e5dba6a
address comment
broxigarchen Mar 3, 2025
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20 changes: 16 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1478,10 +1478,21 @@ bool AMDGPUInstructionSelector::selectG_ICMP_or_FCMP(MachineInstr &I) const {
if (Opcode == -1)
return false;

MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode),
I.getOperand(0).getReg())
.add(I.getOperand(2))
.add(I.getOperand(3));
MachineInstrBuilder ICmp;
// t16 instructions
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0_modifiers)) {
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@Sisyph Sisyph Mar 6, 2025

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This seems less future-proof if instructions are added that don't have src_modifiers on all or none operands, but I guess this will break horribly if it needs an update.

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@broxigarchen broxigarchen Mar 6, 2025

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I can add an assert in the if so that it's more clear when it's broken

ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode), I.getOperand(0).getReg())
.addImm(0)
.add(I.getOperand(2))
.addImm(0)
.add(I.getOperand(3))
.addImm(0); // op_sel
} else {
ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode), I.getOperand(0).getReg())
.add(I.getOperand(2))
.add(I.getOperand(3));
}

RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
*TRI.getBoolRC(), *MRI);
bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
Expand Down Expand Up @@ -4596,6 +4607,7 @@ AMDGPUInstructionSelector::selectVOP3OpSelMods(MachineOperand &Root) const {
}};
}

// FIXME-TRUE16 remove when fake16 is removed
InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVINTERPMods(MachineOperand &Root) const {
Register Src;
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