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[X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors #129042

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Merged
RKSimon merged 2 commits into from
Feb 27, 2025
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[X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors #129042

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[X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors
RKSimon Feb 27, 2025
5985a07
Merge branch 'upstream' into x86-faux-insert_subvector-passthrough
RKSimon Feb 27, 2025
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7 changes: 7 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -6145,6 +6145,13 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
EVT SubVT = Sub.getValueType();
unsigned NumSubElts = SubVT.getVectorNumElements();
uint64_t InsertIdx = N.getConstantOperandVal(2);
// Subvector isn't demanded - just return the base vector.
if (DemandedElts.extractBits(NumSubElts, InsertIdx) == 0) {
Mask.resize(NumElts, SM_SentinelUndef);
std::iota(Mask.begin(), Mask.end(), 0);
Ops.push_back(Src);
return true;
}
// Handle CONCAT(SUB0, SUB1).
// Limit this to vXi64 vector cases to make the most of cross lane shuffles.
if (Depth > 0 && InsertIdx == NumSubElts && NumElts == (2 * NumSubElts) &&
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7 changes: 3 additions & 4 deletions llvm/test/CodeGen/X86/avx-insertelt.ll
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Expand Up @@ -270,11 +270,10 @@ define <16 x i16> @insert_i16_firstelts(<16 x i16> %x, i16 %s) {
; AVX2-LABEL: insert_i16_firstelts:
; AVX2: # %bb.0:
; AVX2-NEXT: vpinsrw $0, %edi, %xmm0, %xmm1
; AVX2-NEXT: vmovd %edi, %xmm2
; AVX2-NEXT: vpbroadcastw %xmm2, %ymm2
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm2[0],ymm0[1,2,3,4,5,6,7],ymm2[8],ymm0[9,10,11,12,13,14,15]
Comment on lines 272 to +275
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@phoebewang phoebewang Feb 27, 2025 •
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Why we do both vpinsrw + vmovd? can't it be:

vpinsrw $0, %edi, %xmm0, %xmm1 OR vmovd %edi, %xmm1
vpbroadcastw %xmm1, %ymm1
vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7],ymm1[8],ymm0[9,10,11,12,13,14,15]

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@RKSimon RKSimon Feb 27, 2025

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LowerINSERT_VECTOR_ELT is very limited on when it uses the broadcast+blend path - I'll see if there's a way to improve it.

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@RKSimon RKSimon Feb 27, 2025

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I've raised #129056

; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
; AVX2-NEXT: vmovd %edi, %xmm1
; AVX2-NEXT: vpbroadcastw %xmm1, %ymm1
; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm0[1,2,3,4,5,6,7],ymm1[8],ymm0[9,10,11,12,13,14,15]
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; AVX2-NEXT: retq
%i0 = insertelement <16 x i16> %x, i16 %s, i32 0
%i1 = insertelement <16 x i16> %i0, i16 %s, i32 8
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12 changes: 5 additions & 7 deletions llvm/test/CodeGen/X86/avx512-insert-extract.ll
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Expand Up @@ -693,20 +693,18 @@ define <16 x i16> @insert_v16i16(<16 x i16> %x, i16 %y, ptr %ptr) nounwind {
; KNL-LABEL: insert_v16i16:
; KNL: ## %bb.0:
; KNL-NEXT: vpinsrw $1, (%rsi), %xmm0, %xmm1
; KNL-NEXT: vmovd %edi, %xmm2
; KNL-NEXT: vpbroadcastw %xmm2, %ymm2
; KNL-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2,3,4,5,6,7,8],ymm2[9],ymm0[10,11,12,13,14,15]
; KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
; KNL-NEXT: vmovd %edi, %xmm1
; KNL-NEXT: vpbroadcastw %xmm1, %ymm1
; KNL-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15]
; KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; KNL-NEXT: retq
;
; SKX-LABEL: insert_v16i16:
; SKX: ## %bb.0:
; SKX-NEXT: vpinsrw $1, (%rsi), %xmm0, %xmm1
; SKX-NEXT: vpbroadcastw %edi, %ymm2
; SKX-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2,3,4,5,6,7,8],ymm2[9],ymm0[10,11,12,13,14,15]
; SKX-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
; SKX-NEXT: vpbroadcastw %edi, %ymm1
; SKX-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15]
; SKX-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; SKX-NEXT: retq
%val = load i16, ptr %ptr
%r1 = insertelement <16 x i16> %x, i16 %val, i32 1
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1,485 changes: 751 additions & 734 deletions llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
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38 changes: 19 additions & 19 deletions llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
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Expand Up @@ -346,26 +346,26 @@ define void @store_i32_stride5_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX-NEXT: vunpcklps {{.*#+}} ymm5 = ymm5[0],ymm6[0],ymm5[1],ymm6[1],ymm5[4],ymm6[4],ymm5[5],ymm6[5]
; AVX-NEXT: vshufpd {{.*#+}} ymm5 = ymm5[0,0,2,3]
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
; AVX-NEXT: vunpcklps {{.*#+}} ymm7 = ymm4[0],ymm1[0],ymm4[1],ymm1[1],ymm4[4],ymm1[4],ymm4[5],ymm1[5]
; AVX-NEXT: vshufpd {{.*#+}} ymm7 = ymm7[0,0,3,3]
; AVX-NEXT: vblendps {{.*#+}} ymm5 = ymm7[0,1],ymm5[2,3],ymm7[4,5,6],ymm5[7]
; AVX-NEXT: vbroadcastf128 {{.*#+}} ymm7 = mem[0,1,0,1]
; AVX-NEXT: vinsertf128 $1, %xmm7, %ymm0, %ymm0
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm5[1,2,3],ymm0[4],ymm5[5,6,7]
; AVX-NEXT: vunpcklps {{.*#+}} ymm4 = ymm4[0],ymm1[0],ymm4[1],ymm1[1],ymm4[4],ymm1[4],ymm4[5],ymm1[5]
; AVX-NEXT: vshufpd {{.*#+}} ymm4 = ymm4[0,0,3,3]
; AVX-NEXT: vblendps {{.*#+}} ymm4 = ymm4[0,1],ymm5[2,3],ymm4[4,5,6],ymm5[7]
; AVX-NEXT: vbroadcastf128 {{.*#+}} ymm5 = mem[0,1,0,1]
; AVX-NEXT: vinsertf128 $1, %xmm5, %ymm0, %ymm7
; AVX-NEXT: vblendps {{.*#+}} ymm4 = ymm7[0],ymm4[1,2,3],ymm7[4],ymm4[5,6,7]
; AVX-NEXT: vpermilps {{.*#+}} ymm1 = ymm1[u,u,u,2,u,u,u,7]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1],ymm4[2],ymm1[3,4,5,6,7]
; AVX-NEXT: vpermilps {{.*#+}} ymm4 = ymm6[1,u,u,u,6,u,u,u]
; AVX-NEXT: vbroadcastss 8(%rcx), %ymm5
; AVX-NEXT: vunpcklps {{.*#+}} ymm4 = ymm4[0],ymm5[0],ymm4[1],ymm5[1],ymm4[4],ymm5[4],ymm4[5],ymm5[5]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1],ymm1[2,3],ymm4[4,5],ymm1[6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm7[1],ymm1[2,3,4,5],ymm7[6],ymm1[7]
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm2[3,3],xmm3[3,3]
; AVX-NEXT: vbroadcastss 12(%rsi), %xmm3
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm2[0,1,2],xmm7[3]
; AVX-NEXT: vmovaps %xmm2, 64(%r9)
; AVX-NEXT: vmovaps %ymm0, (%r9)
; AVX-NEXT: vmovaps %ymm1, 32(%r9)
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4,5,6,7]
; AVX-NEXT: vpermilps {{.*#+}} ymm1 = ymm6[1,u,u,u,6,u,u,u]
; AVX-NEXT: vbroadcastss 8(%rcx), %ymm6
; AVX-NEXT: vunpcklps {{.*#+}} ymm1 = ymm1[0],ymm6[0],ymm1[1],ymm6[1],ymm1[4],ymm6[4],ymm1[5],ymm6[5]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm5[1],ymm0[2,3,4,5],ymm5[6],ymm0[7]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm2[3,3],xmm3[3,3]
; AVX-NEXT: vbroadcastss 12(%rsi), %xmm2
; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[3]
; AVX-NEXT: vmovaps %xmm1, 64(%r9)
; AVX-NEXT: vmovaps %ymm4, (%r9)
; AVX-NEXT: vmovaps %ymm0, 32(%r9)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
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Expand Up @@ -473,7 +473,7 @@ define void @store_i32_stride7_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm8
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm9
; AVX-NEXT: vshufps {{.*#+}} ymm10 = ymm9[1,0],ymm8[1,0],ymm9[5,4],ymm8[5,4]
; AVX-NEXT: vshufps {{.*#+}} ymm10 = ymm10[2,0],ymm8[2,1],ymm10[6,4],ymm8[6,5]
; AVX-NEXT: vshufps {{.*#+}} ymm10 = ymm10[2,0],ymm1[2,1],ymm10[6,4],ymm1[6,5]
; AVX-NEXT: vinsertf128 $1, %xmm5, %ymm6, %ymm5
; AVX-NEXT: vunpckhpd {{.*#+}} ymm6 = ymm7[1],ymm5[1],ymm7[3],ymm5[3]
; AVX-NEXT: vshufps {{.*#+}} ymm6 = ymm5[1,1],ymm6[2,0],ymm5[5,5],ymm6[6,4]
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48 changes: 24 additions & 24 deletions llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
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Expand Up @@ -62,16 +62,16 @@ define void @store_i64_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-NEXT: vmovaps (%rcx), %xmm2
; AVX2-NEXT: vmovaps (%r8), %xmm3
; AVX2-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX2-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX2-NEXT: vunpckhpd {{.*#+}} ymm4 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-NEXT: vpermpd {{.*#+}} ymm4 = ymm4[0,0,2,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm4 = ymm3[0,1],ymm4[2,3,4,5,6,7]
; AVX2-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX2-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm4
; AVX2-NEXT: vunpckhpd {{.*#+}} ymm1 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,0,2,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1],ymm1[2,3,4,5,6,7]
; AVX2-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm4[0],ymm0[2],ymm4[2]
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm2[1],xmm3[1]
; AVX2-NEXT: vmovaps %xmm1, 64(%r9)
; AVX2-NEXT: vunpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1]
; AVX2-NEXT: vmovaps %xmm2, 64(%r9)
; AVX2-NEXT: vmovaps %ymm0, (%r9)
; AVX2-NEXT: vmovaps %ymm4, 32(%r9)
; AVX2-NEXT: vmovaps %ymm1, 32(%r9)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
Expand All @@ -82,16 +82,16 @@ define void @store_i64_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FP-NEXT: vmovaps (%rcx), %xmm2
; AVX2-FP-NEXT: vmovaps (%r8), %xmm3
; AVX2-FP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX2-FP-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX2-FP-NEXT: vunpckhpd {{.*#+}} ymm4 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm4 = ymm4[0,0,2,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm4 = ymm3[0,1],ymm4[2,3,4,5,6,7]
; AVX2-FP-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX2-FP-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm4
; AVX2-FP-NEXT: vunpckhpd {{.*#+}} ymm1 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,0,2,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1],ymm1[2,3,4,5,6,7]
; AVX2-FP-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm4[0],ymm0[2],ymm4[2]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-FP-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm2[1],xmm3[1]
; AVX2-FP-NEXT: vmovaps %xmm1, 64(%r9)
; AVX2-FP-NEXT: vunpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1]
; AVX2-FP-NEXT: vmovaps %xmm2, 64(%r9)
; AVX2-FP-NEXT: vmovaps %ymm0, (%r9)
; AVX2-FP-NEXT: vmovaps %ymm4, 32(%r9)
; AVX2-FP-NEXT: vmovaps %ymm1, 32(%r9)
; AVX2-FP-NEXT: vzeroupper
; AVX2-FP-NEXT: retq
;
Expand All @@ -102,16 +102,16 @@ define void @store_i64_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FCP-NEXT: vmovaps (%rcx), %xmm2
; AVX2-FCP-NEXT: vmovaps (%r8), %xmm3
; AVX2-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX2-FCP-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX2-FCP-NEXT: vunpckhpd {{.*#+}} ymm4 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm4 = ymm4[0,0,2,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm4 = ymm3[0,1],ymm4[2,3,4,5,6,7]
; AVX2-FCP-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX2-FCP-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm4
; AVX2-FCP-NEXT: vunpckhpd {{.*#+}} ymm1 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,0,2,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1],ymm1[2,3,4,5,6,7]
; AVX2-FCP-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm4[0],ymm0[2],ymm4[2]
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-FCP-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm2[1],xmm3[1]
; AVX2-FCP-NEXT: vmovaps %xmm1, 64(%r9)
; AVX2-FCP-NEXT: vunpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1]
; AVX2-FCP-NEXT: vmovaps %xmm2, 64(%r9)
; AVX2-FCP-NEXT: vmovaps %ymm0, (%r9)
; AVX2-FCP-NEXT: vmovaps %ymm4, 32(%r9)
; AVX2-FCP-NEXT: vmovaps %ymm1, 32(%r9)
; AVX2-FCP-NEXT: vzeroupper
; AVX2-FCP-NEXT: retq
;
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72 changes: 36 additions & 36 deletions llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
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Expand Up @@ -79,24 +79,24 @@ define void @store_i64_stride7_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-NEXT: vmovaps (%r8), %xmm2
; AVX2-NEXT: vmovaps (%r9), %xmm3
; AVX2-NEXT: vmovaps (%r10), %xmm4
; AVX2-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX2-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm5
; AVX2-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm5
; AVX2-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1],ymm0[2,3],ymm5[4,5,6,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm5 = ymm5[0,2,2,1]
; AVX2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm6
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm6[0,1],ymm0[2,3],ymm6[4,5,6,7]
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,1]
; AVX2-NEXT: vbroadcastsd %xmm4, %ymm6
; AVX2-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5],ymm5[6,7]
; AVX2-NEXT: vunpckhpd {{.*#+}} ymm6 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm6[4,5],ymm0[6,7]
; AVX2-NEXT: vunpckhpd {{.*#+}} ymm6 = ymm5[1],ymm1[1],ymm5[3],ymm1[3]
; AVX2-NEXT: vpermpd {{.*#+}} ymm6 = ymm6[2,1,3,3]
; AVX2-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm2
; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm6[0,1,2,3,4,5],ymm2[6,7]
; AVX2-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm3[1],xmm4[1]
; AVX2-NEXT: vmovaps %xmm1, 96(%rax)
; AVX2-NEXT: vmovaps %ymm0, (%rax)
; AVX2-NEXT: vunpcklpd {{.*#+}} ymm1 = ymm5[0],ymm1[0],ymm5[2],ymm1[2]
; AVX2-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,1,3]
; AVX2-NEXT: vunpckhpd {{.*#+}} xmm3 = xmm3[1],xmm4[1]
; AVX2-NEXT: vmovaps %xmm3, 96(%rax)
; AVX2-NEXT: vmovaps %ymm1, (%rax)
; AVX2-NEXT: vmovaps %ymm2, 64(%rax)
; AVX2-NEXT: vmovaps %ymm5, 32(%rax)
; AVX2-NEXT: vmovaps %ymm0, 32(%rax)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
Expand All @@ -109,24 +109,24 @@ define void @store_i64_stride7_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FP-NEXT: vmovaps (%r8), %xmm2
; AVX2-FP-NEXT: vmovaps (%r9), %xmm3
; AVX2-FP-NEXT: vmovaps (%r10), %xmm4
; AVX2-FP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX2-FP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm5
; AVX2-FP-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX2-FP-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm5
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1],ymm0[2,3],ymm5[4,5,6,7]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm5 = ymm5[0,2,2,1]
; AVX2-FP-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm6
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm6[0,1],ymm0[2,3],ymm6[4,5,6,7]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,1]
; AVX2-FP-NEXT: vbroadcastsd %xmm4, %ymm6
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5],ymm5[6,7]
; AVX2-FP-NEXT: vunpckhpd {{.*#+}} ymm6 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm6[4,5],ymm0[6,7]
; AVX2-FP-NEXT: vunpckhpd {{.*#+}} ymm6 = ymm5[1],ymm1[1],ymm5[3],ymm1[3]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm6 = ymm6[2,1,3,3]
; AVX2-FP-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm2
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm2 = ymm6[0,1,2,3,4,5],ymm2[6,7]
; AVX2-FP-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-FP-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm3[1],xmm4[1]
; AVX2-FP-NEXT: vmovaps %xmm1, 96(%rax)
; AVX2-FP-NEXT: vmovaps %ymm0, (%rax)
; AVX2-FP-NEXT: vunpcklpd {{.*#+}} ymm1 = ymm5[0],ymm1[0],ymm5[2],ymm1[2]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,1,3]
; AVX2-FP-NEXT: vunpckhpd {{.*#+}} xmm3 = xmm3[1],xmm4[1]
; AVX2-FP-NEXT: vmovaps %xmm3, 96(%rax)
; AVX2-FP-NEXT: vmovaps %ymm1, (%rax)
; AVX2-FP-NEXT: vmovaps %ymm2, 64(%rax)
; AVX2-FP-NEXT: vmovaps %ymm5, 32(%rax)
; AVX2-FP-NEXT: vmovaps %ymm0, 32(%rax)
; AVX2-FP-NEXT: vzeroupper
; AVX2-FP-NEXT: retq
;
Expand All @@ -139,24 +139,24 @@ define void @store_i64_stride7_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FCP-NEXT: vmovaps (%r8), %xmm2
; AVX2-FCP-NEXT: vmovaps (%r9), %xmm3
; AVX2-FCP-NEXT: vmovaps (%r10), %xmm4
; AVX2-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX2-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm5
; AVX2-FCP-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX2-FCP-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm5
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1],ymm0[2,3],ymm5[4,5,6,7]
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm5 = ymm5[0,2,2,1]
; AVX2-FCP-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm6
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm6[0,1],ymm0[2,3],ymm6[4,5,6,7]
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,1]
; AVX2-FCP-NEXT: vbroadcastsd %xmm4, %ymm6
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5],ymm5[6,7]
; AVX2-FCP-NEXT: vunpckhpd {{.*#+}} ymm6 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm6[4,5],ymm0[6,7]
; AVX2-FCP-NEXT: vunpckhpd {{.*#+}} ymm6 = ymm5[1],ymm1[1],ymm5[3],ymm1[3]
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm6 = ymm6[2,1,3,3]
; AVX2-FCP-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm2
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm2 = ymm6[0,1,2,3,4,5],ymm2[6,7]
; AVX2-FCP-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-FCP-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm3[1],xmm4[1]
; AVX2-FCP-NEXT: vmovaps %xmm1, 96(%rax)
; AVX2-FCP-NEXT: vmovaps %ymm0, (%rax)
; AVX2-FCP-NEXT: vunpcklpd {{.*#+}} ymm1 = ymm5[0],ymm1[0],ymm5[2],ymm1[2]
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,1,3]
; AVX2-FCP-NEXT: vunpckhpd {{.*#+}} xmm3 = xmm3[1],xmm4[1]
; AVX2-FCP-NEXT: vmovaps %xmm3, 96(%rax)
; AVX2-FCP-NEXT: vmovaps %ymm1, (%rax)
; AVX2-FCP-NEXT: vmovaps %ymm2, 64(%rax)
; AVX2-FCP-NEXT: vmovaps %ymm5, 32(%rax)
; AVX2-FCP-NEXT: vmovaps %ymm0, 32(%rax)
; AVX2-FCP-NEXT: vzeroupper
; AVX2-FCP-NEXT: retq
;
Expand Down
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