[AggressiveInstCombine] Merge consecutive loads of mixed sizes #129263

Cancelll · 2025-02-28T16:18:32Z

Proof: https://alive2.llvm.org/ce/z/r7M-Sf
Closes: #128134

github-actions · 2025-02-28T16:18:52Z

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llvmbot · 2025-02-28T16:19:24Z

@llvm/pr-subscribers-llvm-transforms

Author: Zhenyang Xu (Cancelll)

Changes

Proof: https://alive2.llvm.org/ce/z/r7M-Sf
Closes: #128134

Patch is 24.99 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/129263.diff

3 Files Affected:

(modified) llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp (+2-2)
(modified) llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll (+210-70)
(modified) llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll (+159-49)

diff --git a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
index fe7b3b1676e08..d610fa8002654 100644
--- a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+++ b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
@@ -675,10 +675,10 @@ static bool foldLoadsRecursive(Value *V, LoadOps &LOps, const DataLayout &DL,
       Load2Ptr->stripAndAccumulateConstantOffsets(DL, Offset2,
                                                   /* AllowNonInbounds */ true);
 
-  // Verify if both loads have same base pointers and load sizes are same.
+  // Verify if both loads have same base pointers
   uint64_t LoadSize1 = LI1->getType()->getPrimitiveSizeInBits();
   uint64_t LoadSize2 = LI2->getType()->getPrimitiveSizeInBits();
-  if (Load1Ptr != Load2Ptr || LoadSize1 != LoadSize2)
+  if (Load1Ptr != Load2Ptr)
     return false;
 
   // Support Loadsizes greater or equal to 8bits and only power of 2.
diff --git a/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll b/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
index 10c4c9b0ca4c9..3e8cb04349583 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
@@ -1529,20 +1529,24 @@ define i64 @eggs(ptr noundef readonly %arg) {
 }
 
 define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
-; ALL-LABEL: @loadCombine_4consecutive_mixsize1(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; ALL-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; ALL-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; ALL-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; ALL-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; ALL-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 16
-; ALL-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 24
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; ALL-NEXT:    ret i32 [[O2]]
+; LE-LABEL: @loadCombine_4consecutive_mixsize1(
+; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
+; LE-NEXT:    ret i32 [[L1]]
+;
+; BE-LABEL: @loadCombine_4consecutive_mixsize1(
+; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; BE-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
+; BE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; BE-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; BE-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
+; BE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
+; BE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
+; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 16
+; BE-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 24
+; BE-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; BE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; BE-NEXT:    ret i32 [[O2]]
 ;
   %p1 = getelementptr i8, ptr %p, i32 2
   %p2 = getelementptr i8, ptr %p, i32 3
@@ -1563,20 +1567,24 @@ define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
 }
 
 define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
-; ALL-LABEL: @loadCombine_4consecutive_mixsize1_BE(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; ALL-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; ALL-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; ALL-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; ALL-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; ALL-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
-; ALL-NEXT:    [[S1:%.*]] = shl i32 [[E1]], 16
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[S1]], [[S2]]
-; ALL-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[E3]]
-; ALL-NEXT:    ret i32 [[O2]]
+; LE-LABEL: @loadCombine_4consecutive_mixsize1_BE(
+; LE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; LE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; LE-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
+; LE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; LE-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; LE-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
+; LE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
+; LE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
+; LE-NEXT:    [[S1:%.*]] = shl i32 [[E1]], 16
+; LE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
+; LE-NEXT:    [[O1:%.*]] = or i32 [[S1]], [[S2]]
+; LE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[E3]]
+; LE-NEXT:    ret i32 [[O2]]
+;
+; BE-LABEL: @loadCombine_4consecutive_mixsize1_BE(
+; BE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
+; BE-NEXT:    ret i32 [[L1]]
 ;
   %p1 = getelementptr i8, ptr %p, i32 2
   %p2 = getelementptr i8, ptr %p, i32 3
@@ -1597,20 +1605,24 @@ define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
 }
 
 define i32 @loadCombine_4consecutive_rev_mixsize1(ptr %p) {
-; ALL-LABEL: @loadCombine_4consecutive_rev_mixsize1(
-; ALL-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; ALL-NEXT:    [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; ALL-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; ALL-NEXT:    [[L2:%.*]] = load i8, ptr [[P2]], align 1
-; ALL-NEXT:    [[L3:%.*]] = load i8, ptr [[P3]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; ALL-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 16
-; ALL-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 24
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[S3]], [[S2]]
-; ALL-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[E1]]
-; ALL-NEXT:    ret i32 [[O2]]
+; LE-LABEL: @loadCombine_4consecutive_rev_mixsize1(
+; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
+; LE-NEXT:    ret i32 [[L1]]
+;
+; BE-LABEL: @loadCombine_4consecutive_rev_mixsize1(
+; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; BE-NEXT:    [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; BE-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
+; BE-NEXT:    [[L2:%.*]] = load i8, ptr [[P2]], align 1
+; BE-NEXT:    [[L3:%.*]] = load i8, ptr [[P3]], align 1
+; BE-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
+; BE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
+; BE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
+; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 16
+; BE-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 24
+; BE-NEXT:    [[O1:%.*]] = or i32 [[S3]], [[S2]]
+; BE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[E1]]
+; BE-NEXT:    ret i32 [[O2]]
 ;
   %p2 = getelementptr i8, ptr %p, i32 2
   %p3 = getelementptr i8, ptr %p, i32 3
@@ -1631,20 +1643,24 @@ define i32 @loadCombine_4consecutive_rev_mixsize1(ptr %p) {
 }
 
 define i32 @loadCombine_4consecutive_rev_mixsize1_BE(ptr %p) {
-; ALL-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
-; ALL-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; ALL-NEXT:    [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; ALL-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; ALL-NEXT:    [[L2:%.*]] = load i8, ptr [[P2]], align 1
-; ALL-NEXT:    [[L3:%.*]] = load i8, ptr [[P3]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; ALL-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
-; ALL-NEXT:    [[S1:%.*]] = shl i32 [[E1]], 16
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E3]], [[S2]]
-; ALL-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S1]]
-; ALL-NEXT:    ret i32 [[O2]]
+; LE-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
+; LE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; LE-NEXT:    [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; LE-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
+; LE-NEXT:    [[L2:%.*]] = load i8, ptr [[P2]], align 1
+; LE-NEXT:    [[L3:%.*]] = load i8, ptr [[P3]], align 1
+; LE-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
+; LE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
+; LE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
+; LE-NEXT:    [[S1:%.*]] = shl i32 [[E1]], 16
+; LE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
+; LE-NEXT:    [[O1:%.*]] = or i32 [[E3]], [[S2]]
+; LE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S1]]
+; LE-NEXT:    ret i32 [[O2]]
+;
+; BE-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
+; BE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
+; BE-NEXT:    ret i32 [[L1]]
 ;
   %p2 = getelementptr i8, ptr %p, i32 2
   %p3 = getelementptr i8, ptr %p, i32 3
@@ -1665,20 +1681,24 @@ define i32 @loadCombine_4consecutive_rev_mixsize1_BE(ptr %p) {
 }
 
 define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
-; ALL-LABEL: @loadCombine_4consecutive_mixsize2(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; ALL-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; ALL-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
-; ALL-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; ALL-NEXT:    [[L3:%.*]] = load i16, ptr [[P2]], align 2
-; ALL-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; ALL-NEXT:    [[E3:%.*]] = zext i16 [[L3]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
-; ALL-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 16
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; ALL-NEXT:    ret i32 [[O2]]
+; LE-LABEL: @loadCombine_4consecutive_mixsize2(
+; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
+; LE-NEXT:    ret i32 [[L1]]
+;
+; BE-LABEL: @loadCombine_4consecutive_mixsize2(
+; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; BE-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
+; BE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; BE-NEXT:    [[L3:%.*]] = load i16, ptr [[P2]], align 2
+; BE-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i32
+; BE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
+; BE-NEXT:    [[E3:%.*]] = zext i16 [[L3]] to i32
+; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
+; BE-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 16
+; BE-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; BE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; BE-NEXT:    ret i32 [[O2]]
 ;
   %p1 = getelementptr i8, ptr %p, i32 1
   %p2 = getelementptr i8, ptr %p, i32 2
@@ -1698,6 +1718,126 @@ define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
   ret i32 %o2
 }
 
+define i32 @loadCombine_4consecutive_mixsize3(ptr %p) {
+; LE-LABEL: @loadCombine_4consecutive_mixsize3(
+; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
+; LE-NEXT:    ret i32 [[L1]]
+;
+; BE-LABEL: @loadCombine_4consecutive_mixsize3(
+; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; BE-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
+; BE-NEXT:    [[L2:%.*]] = load i16, ptr [[P1]], align 2
+; BE-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; BE-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i32
+; BE-NEXT:    [[E2:%.*]] = zext i16 [[L2]] to i32
+; BE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
+; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
+; BE-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 24
+; BE-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; BE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; BE-NEXT:    ret i32 [[O2]]
+;
+  %p1 = getelementptr i8, ptr %p, i32 1
+  %p2 = getelementptr i8, ptr %p, i32 3
+  %l1 = load i8, ptr %p
+  %l2 = load i16, ptr %p1
+  %l3 = load i8, ptr %p2
+
+  %e1 = zext i8 %l1 to i32
+  %e2 = zext i16 %l2 to i32
+  %e3 = zext i8 %l3 to i32
+
+  %s2 = shl i32 %e2, 8
+  %s3 = shl i32 %e3, 24
+
+  %o1 = or i32 %e1, %s2
+  %o2 = or i32 %o1, %s3
+  ret i32 %o2
+}
+
+define i16 @loadCombine_mixsize_4bit(ptr %p) {
+; ALL-LABEL: @loadCombine_mixsize_4bit(
+; ALL-NEXT:    [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 2
+; ALL-NEXT:    [[P2:%.*]] = getelementptr i4, ptr [[P]], i32 3
+; ALL-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT:    [[L2:%.*]] = load i4, ptr [[P1]], align 1
+; ALL-NEXT:    [[L3:%.*]] = load i4, ptr [[P2]], align 1
+; ALL-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i16
+; ALL-NEXT:    [[E2:%.*]] = zext i4 [[L2]] to i16
+; ALL-NEXT:    [[E3:%.*]] = zext i4 [[L3]] to i16
+; ALL-NEXT:    [[S2:%.*]] = shl i16 [[E2]], 8
+; ALL-NEXT:    [[S3:%.*]] = shl i16 [[E3]], 12
+; ALL-NEXT:    [[O1:%.*]] = or i16 [[E1]], [[S2]]
+; ALL-NEXT:    [[O2:%.*]] = or i16 [[O1]], [[S3]]
+; ALL-NEXT:    ret i16 [[O2]]
+;
+  %p1 = getelementptr i4, ptr %p, i32 2
+  %p2 = getelementptr i4, ptr %p, i32 3
+  %l1 = load i8, ptr %p
+  %l2 = load i4, ptr %p1
+  %l3 = load i4, ptr %p2
+
+  %e1 = zext i8 %l1 to i16
+  %e2 = zext i4 %l2 to i16
+  %e3 = zext i4 %l3 to i16
+
+  %s2 = shl i16 %e2, 8
+  %s3 = shl i16 %e3, 12
+
+  %o1 = or i16 %e1, %s2
+  %o2 = or i16 %o1, %s3
+  ret i16 %o2
+}
+
+define i64 @loadCombine_8consecutive_mixsize(ptr %p) {
+; LE-LABEL: @loadCombine_8consecutive_mixsize(
+; LE-NEXT:    [[L1:%.*]] = load i64, ptr [[P:%.*]], align 1
+; LE-NEXT:    ret i64 [[L1]]
+;
+; BE-LABEL: @loadCombine_8consecutive_mixsize(
+; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
+; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2
+; BE-NEXT:    [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 4
+; BE-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
+; BE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; BE-NEXT:    [[L3:%.*]] = load i16, ptr [[P2]], align 2
+; BE-NEXT:    [[L4:%.*]] = load i32, ptr [[P3]], align 4
+; BE-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i64
+; BE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i64
+; BE-NEXT:    [[E3:%.*]] = zext i16 [[L3]] to i64
+; BE-NEXT:    [[E4:%.*]] = zext i32 [[L4]] to i64
+; BE-NEXT:    [[S2:%.*]] = shl i64 [[E2]], 8
+; BE-NEXT:    [[S3:%.*]] = shl i64 [[E3]], 16
+; BE-NEXT:    [[S4:%.*]] = shl i64 [[E4]], 32
+; BE-NEXT:    [[O1:%.*]] = or i64 [[E1]], [[S2]]
+; BE-NEXT:    [[O2:%.*]] = or i64 [[O1]], [[S3]]
+; BE-NEXT:    [[O3:%.*]] = or i64 [[O2]], [[S4]]
+; BE-NEXT:    ret i64 [[O3]]
+;
+  %p1 = getelementptr i8, ptr %p, i64 1
+  %p2 = getelementptr i8, ptr %p, i64 2
+  %p3 = getelementptr i8, ptr %p, i64 4
+  %l1 = load i8, ptr %p
+  %l2 = load i8, ptr %p1
+  %l3 = load i16, ptr %p2
+  %l4 = load i32, ptr %p3
+
+  %e1 = zext i8 %l1 to i64
+  %e2 = zext i8 %l2 to i64
+  %e3 = zext i16 %l3 to i64
+  %e4 = zext i32 %l4 to i64
+
+  %s2 = shl i64 %e2, 8
+  %s3 = shl i64 %e3, 16
+  %s4 = shl i64 %e4, 32
+
+  %o1 = or i64 %e1, %s2
+  %o2 = or i64 %o1, %s3
+  %o3 = or i64 %o2, %s4
+  ret i64 %o3
+}
+
 define i32 @loadCombine_4consecutive_lower_index_comes_before(ptr %p) {
 ; LE-LABEL: @loadCombine_4consecutive_lower_index_comes_before(
 ; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
diff --git a/llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll b/llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
index 1b53c8f71222b..760342b085586 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
@@ -1613,20 +1613,24 @@ define i64 @eggs(ptr noundef readonly %arg) {
 }
 
 define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
-; ALL-LABEL: @loadCombine_4consecutive_mixsize1(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; ALL-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; ALL-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; ALL-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; ALL-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; ALL-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 16
-; ALL-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 24
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; ALL-NEXT:    ret i32 [[O2]]
+; LE-LABEL: @loadCombine_4consecutive_mixsize1(
+; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
+; LE-NEXT:    ret i32 [[L1]]
+;
+; BE-LABEL: @loadCombine_4consecutive_mixsize1(
+; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; BE-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
+; BE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; BE-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; BE-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
+; BE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
+; BE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
+; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 16
+; BE-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 24
+; BE-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; BE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; BE-NEXT:    ret i32 [[O2]]
 ;
   %p1 = getelementptr i8, ptr %p, i32 2
   %p2 = getelementptr i8, ptr %p, i32 3
@@ -1647,20 +1651,24 @@ define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
 }
 
 define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
-; ALL-LABEL: @loadCombine_4consecutive_mixsize1_BE(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; ALL-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; ALL-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; ALL-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; ALL-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; ALL-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
-; ALL-NEXT:    [[S1:%.*]] = shl i32 [[E1]], 16
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[S1]], [[S2]]
-; ALL-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[E3]]
-; ALL-NEXT:    ret i32 [[O2]]
+; LE-LABEL: @loadCombine_4consecutive_mixsize1_BE(
+; LE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; LE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; LE-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
+; LE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; LE-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; LE-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
+; LE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
+; LE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
+; LE-NEXT:    [[S1:%.*]] = shl i32 [[E1]], 16
+; LE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
+; LE-NEXT:    [[O1:%.*]] = or i32 [[S1]], [[S2]]
+; LE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[E3]]
+; LE-NEXT:    ret i32 [[O2]]
+;
+; BE-LABEL: @loadCombine_4consecutive_mixsize1_BE(
+; BE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
+; BE-NEXT:    ret i32 [[L1]]
 ;
   %p1 = getelementptr i8, ptr %p, i32 2
   %p2 = getelementptr i8, ptr %p, i32 3
@@ -1682,13 +1690,7 @@ define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
 
 define i32 @loadCombine_4consecutive_rev_mixsize1(ptr %p) {
 ; LE-LABEL: @loadCombine_4consecutive_rev_mixsize1(
-; LE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; LE-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; LE-NEXT:    [[L2:%.*]] = load i16, ptr [[P2]], align 1
-; LE-NEXT:    [[TMP1:%.*]] = zext i16 [[L2]] to i32
-; LE-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 16
-; LE-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; LE-NEXT:    [[O2:%.*]] = or i32 [[TMP2]], [[E1]]
+; LE-NEXT:    [[O2:%.*]] = load i32, ptr [[P:%.*]], align 2
 ; LE-NEXT:    ret i32 [[O2]]
 ;
 ; BE-LABEL: @loadCombine_4consecutive_rev_mixsize1(
@@ -1741,13 +1743,7 @@ define i32 @loadCombine_4consecutive_rev_mixsize1_BE(ptr %p) {
 ; LE-NEXT:    ret i32 [[O2]]
 ;
 ; BE-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
-; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; BE-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; BE-NEXT:    [[L2:%.*]] = load i16, ptr [[P2]], align 1
-; BE-NEXT:    [[TMP1:%.*]] = zext i16 [[L2]] to i32
-; BE-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; BE-NEXT:    [[S1:%.*]] = shl i32 [[E1]], 16
-; BE-NEXT:    [[O2:%.*]] = or i32 [[TMP1]], [[S1]]
+; BE-NEXT:    [[O2:%.*]] = load i32, ptr [[P:%.*]], align 2
 ; BE-NEXT:    ret i32 [[O2]]
 ;
   %p2 = getelementptr i8, ptr %p, i32 2
@@ -1770,13 +1766,7 @@ define i32 @loadCombine_4consecutive_rev_mi...
[truncated]

Cancelll · 2025-03-01T07:17:01Z

It seems like this potential change was mentioned when the transformation was first proposed.
https://reviews.llvm.org/D127392

In D127392#3807970, @nikic wrote:
From a cursory look it looks fine, I assume @dmgreen has reviewed in detail :)
I have one note (that can be addressed later): There's currently a check that the loads have the same size. Does that mean that if you have a partially folded pattern (e.g. one i16 load plus two i8 loads) that it will not get folded? If so, this seems like something we should relax (later).

bipmis: Thats correct. Currently we are folding loads of same size only in a chain. So for above case if two i8 loads belong to single lower chain they can be folded.
Agreed. This is more to do with a stricter basic implementation first. We can relax this later.

llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp

…of two check.

nikic · 2025-03-02T14:48:29Z

llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp

-  // Support Loadsizes greater or equal to 8bits and only power of 2.
-  if (LoadSize1 < 8 || !isPowerOf2_64(LoadSize1))
+  // Support Loadsizes greater or equal to 8bits.
+  if (LoadSize1 < 8 || LoadSize2 < 8)


I think what you want to check at this point is that typeSizeEqualsStoreSize for both loads. Please make sure that something like i9 plus i23 does not fold.

The sum being a power of two is already covered by the isTypeLegal check (well, or the target has non-pow2 legal integers, in which case there's no reason not to do the fold).

…pose. NFC.

llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp

llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll

llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll

dtcxzyw

LGTM. Thank you!

github-actions · 2025-03-05T08:26:19Z

✅ With the latest revision this PR passed the C/C++ code formatter.

dtcxzyw · 2025-03-05T08:31:48Z

Can you fix the code formatting? I will land this patch if @nikic has no more comments.

nikic

LGTM, thanks!

github-actions · 2025-03-05T10:56:20Z

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Cancelll added 3 commits February 28, 2025 23:52

[InstCombine] Add pre-commit tests. NFC.

343b383

[InstCombine] Handle mixsize consecutive loads

16243e2

[InstCombine] Modify the comment accordingly. NFC.

35098bf

llvmbot added the llvm:transforms label Feb 28, 2025

dtcxzyw requested a review from nikic February 28, 2025 16:59

nikic changed the title ~~[InstCombine] Merge consecutive loads of mixed sizes~~ [AggressiveInstCombine] Merge consecutive loads of mixed sizes Feb 28, 2025

This was referenced Mar 1, 2025

Task submission dtcxzyw/llvm-opt-benchmark#1312

Open

pre-commit: PR129263 dtcxzyw/llvm-opt-benchmark#2180

Closed

dtcxzyw reviewed Mar 1, 2025

View reviewed changes

llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp Outdated Show resolved Hide resolved

Cancelll added 3 commits March 2, 2025 18:06

[AggressiveInstCombine] Add more tests. NFC.

f386a1d

[AggressiveInstCombine] Add check for LoadSize2 and remove the power …

3ca730d

…of two check.

[AggressiveInstCombine] Modify the comment accordingly. NFC.

f45e2db

nikic reviewed Mar 2, 2025

View reviewed changes

Cancelll added 3 commits March 3, 2025 01:04

[AggressiveInstCombine] Rename two tests to more clearly show the pur…

b03986b

…pose. NFC.

[AggressiveInstCombine] Add more negative tests. NFC.

7c7c8fc

[AggressiveInstCombine] Check load sizes equal to store sizes.

f1e2914

nikic reviewed Mar 2, 2025

View reviewed changes

Cancelll added 2 commits March 3, 2025 14:34

[AggressiveInstCombine] Address review comments. NFC.

ad75d16

[AggressiveInstCombine] Remove unnecessarily repeated tests. NFC.

1541a9b

dtcxzyw requested a review from nikic March 5, 2025 06:10

dtcxzyw mentioned this pull request Mar 5, 2025

pre-commit: PR129263 dtcxzyw/llvm-opt-benchmark#2187

Closed

dtcxzyw approved these changes Mar 5, 2025

View reviewed changes

[AggressiveInstCombine] Fix the format issue. NFC.

79aa2da

nikic approved these changes Mar 5, 2025

View reviewed changes

dtcxzyw merged commit a98707e into llvm:main Mar 5, 2025
11 checks passed

[AggressiveInstCombine] Merge consecutive loads of mixed sizes #129263

[AggressiveInstCombine] Merge consecutive loads of mixed sizes #129263

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