[DAG] Cleanup MatchFunnelPosNeg by using SDPatternMatch matchers

[Rajveer100]

No description provided.

[llvmbot]

@llvm/pr-subscribers-llvm-selectiondag

Author: Rajveer Singh Bharadwaj (Rajveer100)

Changes

Resolves #129034

---

Full diff: https://github.com/llvm/llvm-project/pull/129431.diff

1 Files Affected:

• (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+7)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8c51cb3af6142..805c1eec6cac0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8528,6 +8528,13 @@ SDValue DAGCombiner::MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos,
       return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos);
     }
 
+    SDValue X1, Y;
+    if (sd_match(N1, m_Srl(X1, m_SpecificInt(1))) &&
+        sd_match(InnerNeg, m_Xor(Y, m_SpecificInt(EltBits - 1))) &&
+        Y == InnerPos && TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) {
+      return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos);
+    }
+
     // fold (or (shl (shl x0, 1), (xor y, 31)), (srl x1, y))
     //   -> (fshr x0, x1, y)
     if (IsBinOpImm(N0, ISD::SHL, 1) &&

[Rajveer100]

@RKSimon
I am not quite sure if this is in the right direction.

[RKSimon]

You can remove Y and use m_Specific(InnerPos)

[RKSimon]

This should be removed entirely

[RKSimon]

N1.getOperand(0) -> X1

[RKSimon]

X1 -> m_Value(X1)