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@4vtomat 4vtomat commented Mar 3, 2025

This is introduced in 39ec9de

@llvmbot llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. labels Mar 3, 2025
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llvmbot commented Mar 3, 2025

@llvm/pr-subscribers-clang
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang-codegen

Author: Brandon Wu (4vtomat)

Changes

This is introduced in 39ec9de


Full diff: https://github.com/llvm/llvm-project/pull/129493.diff

1 Files Affected:

  • (modified) clang/lib/CodeGen/Targets/RISCV.cpp (+3-1)
diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp
index 109fa1f9ee521..e350a3589dcaf 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -578,7 +578,9 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty, unsigned ABIVLen) const {
   } else {
     // Check registers needed <= 8.
     if ((EltType->getScalarSizeInBits() * NumElts / ABIVLen) > 8)
-      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
+      return getNaturalAlignIndirect(
+          Ty, /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),
+          /*ByVal=*/false);
 
     // Generic vector
     // The number of elements needs to be at least 1.

@4vtomat 4vtomat merged commit 1119b72 into llvm:main Mar 3, 2025
15 checks passed
@4vtomat 4vtomat deleted the riscv_addr_space_arg branch March 3, 2025 09:38
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