diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td index e7f8f88e3909f..1ac05c9444725 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td @@ -22,6 +22,8 @@ class SiFiveP400IsWorstCaseMXSEW MxList, bit is bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW)); } +defvar SiFiveP400VLEN = 128; + // 1 Micro-Op per cycle. class SiFiveP400GetLMulCycles { int c = !cond( @@ -35,19 +37,31 @@ class SiFiveP400GetLMulCycles { ); } -// Latency for segmented loads and stores are calculated as vl * nf. -class SiFiveP400GetCyclesSegmented { - defvar VLEN = 128; - defvar VLUpperBound = !cond( - !eq(mx, "M1") : !div(VLEN, sew), - !eq(mx, "M2") : !div(!mul(VLEN, 2), sew), - !eq(mx, "M4") : !div(!mul(VLEN, 4), sew), - !eq(mx, "M8") : !div(!mul(VLEN, 8), sew), - !eq(mx, "MF2") : !div(!div(VLEN, 2), sew), - !eq(mx, "MF4") : !div(!div(VLEN, 4), sew), - !eq(mx, "MF8") : !div(!div(VLEN, 8), sew), +class SiFiveP400GetVLMAX { + defvar LMUL = SiFiveP400GetLMulCycles.c; + int val = !cond( + !eq(mx, "MF2") : !div(!div(SiFiveP400VLEN, 2), sew), + !eq(mx, "MF4") : !div(!div(SiFiveP400VLEN, 4), sew), + !eq(mx, "MF8") : !div(!div(SiFiveP400VLEN, 8), sew), + true: !div(!mul(SiFiveP400VLEN, LMUL), sew) + ); +} + +class SiFiveP400StridedLdStLatency { + defvar VL = SiFiveP400GetVLMAX.val; + int val = !cond( + !eq(VL, 2): 13, + !eq(VL, 4): 18, + !eq(VL, 8): 22, + !eq(VL, 16): 30, + // VL=32,64,128 + true: !sub(VL, 2) ); - int c = !mul(VLUpperBound, nf); +} + +// Latency for segmented loads and stores are calculated as vl * nf. +class SiFiveP400SegmentedLdStCycles { + int c = !mul(SiFiveP400GetVLMAX.val, nf); } // Both variants of floating point vector reductions are based on numbers collected @@ -368,57 +382,37 @@ def : WriteRes; def : WriteRes; // 7. Vector Loads and Stores -// FIXME: This unit is still being improved, currently -// it is based on stage numbers. Estimates are optimistic, -// latency may be longer. -foreach mx = SchedMxList in { - defvar LMulLat = SiFiveP400GetLMulCycles.c; - defvar IsWorstCase = SiFiveP400IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP400VLD], mx, IsWorstCase>; - } - let Latency = 12, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVLDS8", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDS16", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDS32", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDS64", [SiFiveP400VLD], mx, IsWorstCase>; - } - let Latency = 12, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFiveP400VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFiveP400VLD], mx, IsWorstCase>; - } -} +// Note that the latency of vector loads are measured by consuming the loaded +// value with vmv.x.s before subtracting the latency of vmv.x.s from the number. foreach mx = SchedMxList in { defvar LMulLat = SiFiveP400GetLMulCycles.c; defvar IsWorstCase = SiFiveP400IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP400VST], mx, IsWorstCase>; - } - let Latency = 12, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVSTS8", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTS16", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTS32", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTS64", [SiFiveP400VST], mx, IsWorstCase>; + let Latency = 8 in { + let ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP400VLD], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP400VLD], mx, IsWorstCase>; + + defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP400VST], mx, IsWorstCase>; + } + + // Mask load and store have a maximum EMUL of 1. + let ReleaseAtCycles = [SiFiveP400GetLMulCycles<"M1">.c] in { + defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP400VLD], mx, IsWorstCase=!eq(mx, "M1")>; + defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP400VST], mx, IsWorstCase=!eq(mx, "M1")>; + } } - let Latency = 12, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFiveP400VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFiveP400VST], mx, IsWorstCase>; + foreach eew = [8, 16, 32, 64] in { + let Latency = SiFiveP400StridedLdStLatency.val, + ReleaseAtCycles = [SiFiveP400GetVLMAX.val] in { + defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SiFiveP400VLD], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SiFiveP400VLD], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SiFiveP400VLD], mx, IsWorstCase>; + + defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SiFiveP400VST], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SiFiveP400VST], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SiFiveP400VST], mx, IsWorstCase>; + } } } @@ -426,7 +420,7 @@ foreach mx = SchedMxList in { foreach nf=2-8 in { foreach eew = [8, 16, 32, 64] in { defvar IsWorstCase = SiFiveP400IsWorstCaseMX.c; - defvar LMulLat = SiFiveP400GetCyclesSegmented.c; + defvar LMulLat = SiFiveP400SegmentedLdStCycles.c; let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in { defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td index 60d41b02f0e8a..2bfd5ef811c7b 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td @@ -22,6 +22,8 @@ class SiFiveP600IsWorstCaseMXSEW MxList, bit is bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW)); } +defvar SiFiveP600VLEN = 128; + // 1 Micro-Op per cycle. class SiFiveP600GetLMulCycles { int c = !cond( @@ -35,19 +37,31 @@ class SiFiveP600GetLMulCycles { ); } -// Latency for segmented loads and stores are calculated as vl * nf. -class SiFiveP600GetCyclesSegmented { - defvar VLEN = 128; - defvar VLUpperBound = !cond( - !eq(mx, "M1") : !div(VLEN, sew), - !eq(mx, "M2") : !div(!mul(VLEN, 2), sew), - !eq(mx, "M4") : !div(!mul(VLEN, 4), sew), - !eq(mx, "M8") : !div(!mul(VLEN, 8), sew), - !eq(mx, "MF2") : !div(!div(VLEN, 2), sew), - !eq(mx, "MF4") : !div(!div(VLEN, 4), sew), - !eq(mx, "MF8") : !div(!div(VLEN, 8), sew), +class SiFiveP600GetVLMAX { + defvar LMUL = SiFiveP600GetLMulCycles.c; + int val = !cond( + !eq(mx, "MF2") : !div(!div(SiFiveP600VLEN, 2), sew), + !eq(mx, "MF4") : !div(!div(SiFiveP600VLEN, 4), sew), + !eq(mx, "MF8") : !div(!div(SiFiveP600VLEN, 8), sew), + true: !div(!mul(SiFiveP600VLEN, LMUL), sew) + ); +} + +class SiFiveP600StridedLdStLatency { + defvar VL = SiFiveP400GetVLMAX.val; + int val = !cond( + !eq(VL, 2): 13, + !eq(VL, 4): 18, + !eq(VL, 8): 22, + !eq(VL, 16): 30, + // VL=32,64,128 + true: !sub(VL, 2) ); - int c = !mul(VLUpperBound, nf); +} + +// Latency for segmented loads and stores are calculated as vl * nf. +class SiFiveP600SegmentedLdStCycles { + int c = !mul(SiFiveP600GetVLMAX.val, nf); } class SiFiveP600VSM3CCycles { @@ -544,64 +558,44 @@ def : WriteRes; def : WriteRes; // 7. Vector Loads and Stores -// FIXME: This unit is still being improved, currently -// it is based on stage numbers. Estimates are optimistic, -// latency may be longer. -foreach mx = SchedMxList in { - defvar LMulLat = SiFiveP600GetLMulCycles.c; - defvar IsWorstCase = SiFiveP600IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP600VLD], mx, IsWorstCase>; - } - let Latency = 12, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVLDS8", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDS16", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDS32", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDS64", [SiFiveP600VLD], mx, IsWorstCase>; - } - let Latency = 12, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFiveP600VLD], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFiveP600VLD], mx, IsWorstCase>; - } -} +// Note that the latency of vector loads are measured by consuming the loaded +// value with vmv.x.s before subtracting the latency of vmv.x.s from the number. foreach mx = SchedMxList in { defvar LMulLat = SiFiveP600GetLMulCycles.c; defvar IsWorstCase = SiFiveP600IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP600VST], mx, IsWorstCase>; - } - let Latency = 12, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVSTS8", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTS16", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTS32", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTS64", [SiFiveP600VST], mx, IsWorstCase>; + let Latency = 8 in { + let ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP600VLD], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP600VLD], mx, IsWorstCase>; + + defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP600VST], mx, IsWorstCase>; + } + + // Mask load and store have a maximum EMUL of 1. + let ReleaseAtCycles = [SiFiveP600GetLMulCycles<"M1">.c] in { + defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP600VLD], mx, IsWorstCase=!eq(mx,"M1")>; + defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP600VST], mx, IsWorstCase=!eq(mx,"M1")>; + } } - let Latency = 12, ReleaseAtCycles = [LMulLat] in { - defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFiveP600VST], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFiveP600VST], mx, IsWorstCase>; + foreach eew = [8, 16, 32, 64] in { + let Latency = SiFiveP600StridedLdStLatency.val, + ReleaseAtCycles = [SiFiveP600GetVLMAX.val] in { + defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SiFiveP600VLD], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SiFiveP600VLD], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SiFiveP600VLD], mx, IsWorstCase>; + + defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SiFiveP600VST], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SiFiveP600VST], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SiFiveP600VST], mx, IsWorstCase>; + } } } foreach mx = SchedMxList in { foreach nf=2-8 in { foreach eew = [8, 16, 32, 64] in { - defvar LMulLat = SiFiveP600GetCyclesSegmented.c; + defvar LMulLat = SiFiveP600SegmentedLdStCycles.c; defvar IsWorstCase = SiFiveP600IsWorstCaseMX.c; let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in { defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>; diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s new file mode 100644 index 0000000000000..53bf836263759 --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s @@ -0,0 +1,542 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s + +vsetvli zero, zero, e8, mf8, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vle8.v v8, (a0) + +vsetvli zero, zero, e16, mf4, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, mf2, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, m1, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, m2, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, m4, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, m8, ta, ma +vle16.v v8, (a0) + +vsetvli zero, zero, e32, mf2, ta, ma +vle32.v v8, (a0) +vsetvli zero, zero, e32, m1, ta, ma +vle32.v v8, (a0) +vsetvli zero, zero, e32, m2, ta, ma +vle32.v v8, (a0) +vsetvli zero, zero, e32, m4, ta, ma +vle32.v v8, (a0) +vsetvli zero, zero, e32, m8, ta, ma +vle32.v v8, (a0) + +vsetvli zero, zero, e64, m1, ta, ma +vle64.v v8, (a0) +vsetvli zero, zero, e64, m2, ta, ma +vle64.v v8, (a0) +vsetvli zero, zero, e64, m4, ta, ma +vle64.v v8, (a0) +vsetvli zero, zero, e64, m8, ta, ma +vle64.v v8, (a0) + +vsetvli zero, zero, e8, mf8, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vse8.v v8, (a0) + +vsetvli zero, zero, e16, mf4, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, mf2, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, m1, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, m2, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, m4, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, m8, ta, ma +vse16.v v8, (a0) + +vsetvli zero, zero, e32, mf2, ta, ma +vse32.v v8, (a0) +vsetvli zero, zero, e32, m1, ta, ma +vse32.v v8, (a0) +vsetvli zero, zero, e32, m2, ta, ma +vse32.v v8, (a0) +vsetvli zero, zero, e32, m4, ta, ma +vse32.v v8, (a0) +vsetvli zero, zero, e32, m8, ta, ma +vse32.v v8, (a0) + +vsetvli zero, zero, e64, m1, ta, ma +vse64.v v8, (a0) +vsetvli zero, zero, e64, m2, ta, ma +vse64.v v8, (a0) +vsetvli zero, zero, e64, m4, ta, ma +vse64.v v8, (a0) +vsetvli zero, zero, e64, m8, ta, ma +vse64.v v8, (a0) + +# Unit-stride mask load/store + +vsetvli zero, zero, e8, mf8, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vlm.v v8, (a0) + +vsetvli zero, zero, e8, mf8, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vsm.v v8, (a0) + +# Fault-only-first + +vsetvli zero, zero, e8, mf8, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vle8ff.v v8, (a0) + +vsetvli zero, zero, e16, mf4, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, mf2, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, m1, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, m2, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, m4, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, m8, ta, ma +vle16ff.v v8, (a0) + +vsetvli zero, zero, e32, mf2, ta, ma +vle32ff.v v8, (a0) +vsetvli zero, zero, e32, m1, ta, ma +vle32ff.v v8, (a0) +vsetvli zero, zero, e32, m2, ta, ma +vle32ff.v v8, (a0) +vsetvli zero, zero, e32, m4, ta, ma +vle32ff.v v8, (a0) +vsetvli zero, zero, e32, m8, ta, ma +vle32ff.v v8, (a0) + +vsetvli zero, zero, e64, m1, ta, ma +vle64ff.v v8, (a0) +vsetvli zero, zero, e64, m2, ta, ma +vle64ff.v v8, (a0) +vsetvli zero, zero, e64, m4, ta, ma +vle64ff.v v8, (a0) +vsetvli zero, zero, e64, m8, ta, ma +vle64ff.v v8, (a0) + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 160 +# CHECK-NEXT: Total Cycles: 146 +# CHECK-NEXT: Total uOps: 160 + +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.10 +# CHECK-NEXT: IPC: 1.10 +# CHECK-NEXT: Block RThroughput: 139.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vse64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vse64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vse64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle64ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle64ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle64ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle64ff.v v8, (a0) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFiveP400Div +# CHECK-NEXT: [1] - SiFiveP400FEXQ0 +# CHECK-NEXT: [2] - SiFiveP400FloatDiv +# CHECK-NEXT: [3] - SiFiveP400IEXQ0 +# CHECK-NEXT: [4] - SiFiveP400IEXQ1 +# CHECK-NEXT: [5] - SiFiveP400IEXQ2 +# CHECK-NEXT: [6] - SiFiveP400Load +# CHECK-NEXT: [7] - SiFiveP400Store +# CHECK-NEXT: [8] - SiFiveP400VDiv +# CHECK-NEXT: [9] - SiFiveP400VEXQ0 +# CHECK-NEXT: [10] - SiFiveP400VFloatDiv +# CHECK-NEXT: [11] - SiFiveP400VLD +# CHECK-NEXT: [12] - SiFiveP400VST + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] +# CHECK-NEXT: - - - - 80.00 - - - - - - 139.00 73.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0) diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s new file mode 100644 index 0000000000000..fcf544395db8f --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s @@ -0,0 +1,316 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s + +vsetvli zero, zero, e8, mf8, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, mf4, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, mf2, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m1, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m2, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m4, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m8, ta, ma +vlse8.v v8, (a0), t0 + +vsetvli zero, zero, e16, mf4, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, mf2, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m1, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m2, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m4, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m8, ta, ma +vlse16.v v8, (a0), t0 + +vsetvli zero, zero, e32, mf2, ta, ma +vlse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m1, ta, ma +vlse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m2, ta, ma +vlse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m4, ta, ma +vlse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m8, ta, ma +vlse32.v v8, (a0), t0 + +vsetvli zero, zero, e64, m1, ta, ma +vlse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m2, ta, ma +vlse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m4, ta, ma +vlse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m8, ta, ma +vlse64.v v8, (a0), t0 + +vsetvli zero, zero, e8, mf8, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, mf4, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, mf2, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m1, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m2, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m4, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m8, ta, ma +vsse8.v v8, (a0), t0 + +vsetvli zero, zero, e16, mf4, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, mf2, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m1, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m2, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m4, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m8, ta, ma +vsse16.v v8, (a0), t0 + +vsetvli zero, zero, e32, mf2, ta, ma +vsse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m1, ta, ma +vsse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m2, ta, ma +vsse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m4, ta, ma +vsse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m8, ta, ma +vsse32.v v8, (a0), t0 + +vsetvli zero, zero, e64, m1, ta, ma +vsse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m2, ta, ma +vsse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m4, ta, ma +vsse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m8, ta, ma +vsse64.v v8, (a0), t0 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 88 +# CHECK-NEXT: Total Cycles: 954 +# CHECK-NEXT: Total uOps: 88 + +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.09 +# CHECK-NEXT: IPC: 0.09 +# CHECK-NEXT: Block RThroughput: 472.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vlse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vlse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vlse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vlse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsse64.v v8, (a0), t0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFiveP400Div +# CHECK-NEXT: [1] - SiFiveP400FEXQ0 +# CHECK-NEXT: [2] - SiFiveP400FloatDiv +# CHECK-NEXT: [3] - SiFiveP400IEXQ0 +# CHECK-NEXT: [4] - SiFiveP400IEXQ1 +# CHECK-NEXT: [5] - SiFiveP400IEXQ2 +# CHECK-NEXT: [6] - SiFiveP400Load +# CHECK-NEXT: [7] - SiFiveP400Store +# CHECK-NEXT: [8] - SiFiveP400VDiv +# CHECK-NEXT: [9] - SiFiveP400VEXQ0 +# CHECK-NEXT: [10] - SiFiveP400VFloatDiv +# CHECK-NEXT: [11] - SiFiveP400VLD +# CHECK-NEXT: [12] - SiFiveP400VST + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] +# CHECK-NEXT: - - - - 44.00 - - - - - - 472.00 472.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 64.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 128.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 64.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse64.v v8, (a0), t0 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s new file mode 100644 index 0000000000000..086dd524ba812 --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s @@ -0,0 +1,588 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s + +vsetvli zero, zero, e8, mf8, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf4, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf2, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m1, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m2, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m4, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m8, ta, ma +vluxei8.v v8, (a0), v0 + +vsetvli zero, zero, e16, mf4, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, mf2, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m1, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m2, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m4, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m8, ta, ma +vluxei16.v v8, (a0), v0 + +vsetvli zero, zero, e32, mf2, ta, ma +vluxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m1, ta, ma +vluxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m2, ta, ma +vluxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m4, ta, ma +vluxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m8, ta, ma +vluxei32.v v8, (a0), v0 + +vsetvli zero, zero, e64, m1, ta, ma +vluxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m2, ta, ma +vluxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m4, ta, ma +vluxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m8, ta, ma +vluxei64.v v8, (a0), v0 + +vsetvli zero, zero, e8, mf8, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf4, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf2, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m1, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m2, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m4, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m8, ta, ma +vloxei8.v v8, (a0), v0 + +vsetvli zero, zero, e16, mf4, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, mf2, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m1, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m2, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m4, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m8, ta, ma +vloxei16.v v8, (a0), v0 + +vsetvli zero, zero, e32, mf2, ta, ma +vloxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m1, ta, ma +vloxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m2, ta, ma +vloxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m4, ta, ma +vloxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m8, ta, ma +vloxei32.v v8, (a0), v0 + +vsetvli zero, zero, e64, m1, ta, ma +vloxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m2, ta, ma +vloxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m4, ta, ma +vloxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m8, ta, ma +vloxei64.v v8, (a0), v0 + +vsetvli zero, zero, e8, mf8, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf4, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf2, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m1, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m2, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m4, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m8, ta, ma +vsuxei8.v v8, (a0), v0 + +vsetvli zero, zero, e16, mf4, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, mf2, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m1, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m2, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m4, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m8, ta, ma +vsuxei16.v v8, (a0), v0 + +vsetvli zero, zero, e32, mf2, ta, ma +vsuxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m1, ta, ma +vsuxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m2, ta, ma +vsuxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m4, ta, ma +vsuxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m8, ta, ma +vsuxei32.v v8, (a0), v0 + +vsetvli zero, zero, e64, m1, ta, ma +vsuxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m2, ta, ma +vsuxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m4, ta, ma +vsuxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m8, ta, ma +vsuxei64.v v8, (a0), v0 + +vsetvli zero, zero, e8, mf8, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf4, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf2, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m1, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m2, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m4, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m8, ta, ma +vsoxei8.v v8, (a0), v0 + +vsetvli zero, zero, e16, mf4, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, mf2, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m1, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m2, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m4, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m8, ta, ma +vsoxei16.v v8, (a0), v0 + +vsetvli zero, zero, e32, mf2, ta, ma +vsoxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m1, ta, ma +vsoxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m2, ta, ma +vsoxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m4, ta, ma +vsoxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m8, ta, ma +vsoxei32.v v8, (a0), v0 + +vsetvli zero, zero, e64, m1, ta, ma +vsoxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m2, ta, ma +vsoxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m4, ta, ma +vsoxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m8, ta, ma +vsoxei64.v v8, (a0), v0 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 176 +# CHECK-NEXT: Total Cycles: 1898 +# CHECK-NEXT: Total uOps: 176 + +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.09 +# CHECK-NEXT: IPC: 0.09 +# CHECK-NEXT: Block RThroughput: 944.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vluxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vluxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vluxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vluxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vloxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vloxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vloxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vloxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsoxei64.v v8, (a0), v0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFiveP400Div +# CHECK-NEXT: [1] - SiFiveP400FEXQ0 +# CHECK-NEXT: [2] - SiFiveP400FloatDiv +# CHECK-NEXT: [3] - SiFiveP400IEXQ0 +# CHECK-NEXT: [4] - SiFiveP400IEXQ1 +# CHECK-NEXT: [5] - SiFiveP400IEXQ2 +# CHECK-NEXT: [6] - SiFiveP400Load +# CHECK-NEXT: [7] - SiFiveP400Store +# CHECK-NEXT: [8] - SiFiveP400VDiv +# CHECK-NEXT: [9] - SiFiveP400VEXQ0 +# CHECK-NEXT: [10] - SiFiveP400VFloatDiv +# CHECK-NEXT: [11] - SiFiveP400VLD +# CHECK-NEXT: [12] - SiFiveP400VST + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] +# CHECK-NEXT: - - - - 88.00 - - - - - - 944.00 944.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 64.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 128.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 64.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 64.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 128.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 64.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei64.v v8, (a0), v0 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s new file mode 100644 index 0000000000000..cc972c6d63454 --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s @@ -0,0 +1,545 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s + +vsetvli zero, zero, e8, mf8, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vle8.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vle8.v v8, (a0) + +vsetvli zero, zero, e16, mf4, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, mf2, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, m1, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, m2, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, m4, ta, ma +vle16.v v8, (a0) +vsetvli zero, zero, e16, m8, ta, ma +vle16.v v8, (a0) + +vsetvli zero, zero, e32, mf2, ta, ma +vle32.v v8, (a0) +vsetvli zero, zero, e32, m1, ta, ma +vle32.v v8, (a0) +vsetvli zero, zero, e32, m2, ta, ma +vle32.v v8, (a0) +vsetvli zero, zero, e32, m4, ta, ma +vle32.v v8, (a0) +vsetvli zero, zero, e32, m8, ta, ma +vle32.v v8, (a0) + +vsetvli zero, zero, e64, m1, ta, ma +vle64.v v8, (a0) +vsetvli zero, zero, e64, m2, ta, ma +vle64.v v8, (a0) +vsetvli zero, zero, e64, m4, ta, ma +vle64.v v8, (a0) +vsetvli zero, zero, e64, m8, ta, ma +vle64.v v8, (a0) + +vsetvli zero, zero, e8, mf8, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vse8.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vse8.v v8, (a0) + +vsetvli zero, zero, e16, mf4, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, mf2, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, m1, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, m2, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, m4, ta, ma +vse16.v v8, (a0) +vsetvli zero, zero, e16, m8, ta, ma +vse16.v v8, (a0) + +vsetvli zero, zero, e32, mf2, ta, ma +vse32.v v8, (a0) +vsetvli zero, zero, e32, m1, ta, ma +vse32.v v8, (a0) +vsetvli zero, zero, e32, m2, ta, ma +vse32.v v8, (a0) +vsetvli zero, zero, e32, m4, ta, ma +vse32.v v8, (a0) +vsetvli zero, zero, e32, m8, ta, ma +vse32.v v8, (a0) + +vsetvli zero, zero, e64, m1, ta, ma +vse64.v v8, (a0) +vsetvli zero, zero, e64, m2, ta, ma +vse64.v v8, (a0) +vsetvli zero, zero, e64, m4, ta, ma +vse64.v v8, (a0) +vsetvli zero, zero, e64, m8, ta, ma +vse64.v v8, (a0) + +# Unit-stride mask load/store + +vsetvli zero, zero, e8, mf8, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vlm.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vlm.v v8, (a0) + +vsetvli zero, zero, e8, mf8, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vsm.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vsm.v v8, (a0) + +# Fault-only-first + +vsetvli zero, zero, e8, mf8, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, mf4, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, mf2, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, m1, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, m2, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, m4, ta, ma +vle8ff.v v8, (a0) +vsetvli zero, zero, e8, m8, ta, ma +vle8ff.v v8, (a0) + +vsetvli zero, zero, e16, mf4, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, mf2, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, m1, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, m2, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, m4, ta, ma +vle16ff.v v8, (a0) +vsetvli zero, zero, e16, m8, ta, ma +vle16ff.v v8, (a0) + +vsetvli zero, zero, e32, mf2, ta, ma +vle32ff.v v8, (a0) +vsetvli zero, zero, e32, m1, ta, ma +vle32ff.v v8, (a0) +vsetvli zero, zero, e32, m2, ta, ma +vle32ff.v v8, (a0) +vsetvli zero, zero, e32, m4, ta, ma +vle32ff.v v8, (a0) +vsetvli zero, zero, e32, m8, ta, ma +vle32ff.v v8, (a0) + +vsetvli zero, zero, e64, m1, ta, ma +vle64ff.v v8, (a0) +vsetvli zero, zero, e64, m2, ta, ma +vle64ff.v v8, (a0) +vsetvli zero, zero, e64, m4, ta, ma +vle64ff.v v8, (a0) +vsetvli zero, zero, e64, m8, ta, ma +vle64ff.v v8, (a0) + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 160 +# CHECK-NEXT: Total Cycles: 146 +# CHECK-NEXT: Total uOps: 160 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.10 +# CHECK-NEXT: IPC: 1.10 +# CHECK-NEXT: Block RThroughput: 139.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vse8.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vse16.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vse32.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vse64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vse64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vse64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vse64.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle8ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle16ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle32ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 8 1.00 * vle64ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 8 2.00 * vle64ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 8 4.00 * vle64ff.v v8, (a0) +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 8 8.00 * vle64ff.v v8, (a0) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFiveP600Div +# CHECK-NEXT: [1] - SiFiveP600FEXQ0 +# CHECK-NEXT: [2] - SiFiveP600FEXQ1 +# CHECK-NEXT: [3] - SiFiveP600FloatDiv +# CHECK-NEXT: [4] - SiFiveP600IEXQ0 +# CHECK-NEXT: [5] - SiFiveP600IEXQ1 +# CHECK-NEXT: [6] - SiFiveP600IEXQ2 +# CHECK-NEXT: [7] - SiFiveP600IEXQ3 +# CHECK-NEXT: [8.0] - SiFiveP600LDST +# CHECK-NEXT: [8.1] - SiFiveP600LDST +# CHECK-NEXT: [9] - SiFiveP600VDiv +# CHECK-NEXT: [10] - SiFiveP600VEXQ0 +# CHECK-NEXT: [11] - SiFiveP600VEXQ1 +# CHECK-NEXT: [12] - SiFiveP600VFloatDiv +# CHECK-NEXT: [13] - SiFiveP600VLD +# CHECK-NEXT: [14] - SiFiveP600VST + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] +# CHECK-NEXT: - - - - 80.00 - - - - - - - - - 139.00 73.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions: +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse8.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse16.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse32.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse64.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0) +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0) diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s new file mode 100644 index 0000000000000..418eda5f3b145 --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s @@ -0,0 +1,319 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s + +vsetvli zero, zero, e8, mf8, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, mf4, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, mf2, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m1, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m2, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m4, ta, ma +vlse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m8, ta, ma +vlse8.v v8, (a0), t0 + +vsetvli zero, zero, e16, mf4, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, mf2, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m1, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m2, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m4, ta, ma +vlse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m8, ta, ma +vlse16.v v8, (a0), t0 + +vsetvli zero, zero, e32, mf2, ta, ma +vlse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m1, ta, ma +vlse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m2, ta, ma +vlse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m4, ta, ma +vlse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m8, ta, ma +vlse32.v v8, (a0), t0 + +vsetvli zero, zero, e64, m1, ta, ma +vlse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m2, ta, ma +vlse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m4, ta, ma +vlse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m8, ta, ma +vlse64.v v8, (a0), t0 + +vsetvli zero, zero, e8, mf8, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, mf4, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, mf2, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m1, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m2, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m4, ta, ma +vsse8.v v8, (a0), t0 +vsetvli zero, zero, e8, m8, ta, ma +vsse8.v v8, (a0), t0 + +vsetvli zero, zero, e16, mf4, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, mf2, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m1, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m2, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m4, ta, ma +vsse16.v v8, (a0), t0 +vsetvli zero, zero, e16, m8, ta, ma +vsse16.v v8, (a0), t0 + +vsetvli zero, zero, e32, mf2, ta, ma +vsse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m1, ta, ma +vsse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m2, ta, ma +vsse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m4, ta, ma +vsse32.v v8, (a0), t0 +vsetvli zero, zero, e32, m8, ta, ma +vsse32.v v8, (a0), t0 + +vsetvli zero, zero, e64, m1, ta, ma +vsse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m2, ta, ma +vsse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m4, ta, ma +vsse64.v v8, (a0), t0 +vsetvli zero, zero, e64, m8, ta, ma +vsse64.v v8, (a0), t0 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 88 +# CHECK-NEXT: Total Cycles: 954 +# CHECK-NEXT: Total uOps: 88 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.09 +# CHECK-NEXT: IPC: 0.09 +# CHECK-NEXT: Block RThroughput: 472.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vlse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vlse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vlse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vlse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vlse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vlse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vlse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vsse8.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsse16.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsse32.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsse64.v v8, (a0), t0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsse64.v v8, (a0), t0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFiveP600Div +# CHECK-NEXT: [1] - SiFiveP600FEXQ0 +# CHECK-NEXT: [2] - SiFiveP600FEXQ1 +# CHECK-NEXT: [3] - SiFiveP600FloatDiv +# CHECK-NEXT: [4] - SiFiveP600IEXQ0 +# CHECK-NEXT: [5] - SiFiveP600IEXQ1 +# CHECK-NEXT: [6] - SiFiveP600IEXQ2 +# CHECK-NEXT: [7] - SiFiveP600IEXQ3 +# CHECK-NEXT: [8.0] - SiFiveP600LDST +# CHECK-NEXT: [8.1] - SiFiveP600LDST +# CHECK-NEXT: [9] - SiFiveP600VDiv +# CHECK-NEXT: [10] - SiFiveP600VEXQ0 +# CHECK-NEXT: [11] - SiFiveP600VEXQ1 +# CHECK-NEXT: [12] - SiFiveP600VFloatDiv +# CHECK-NEXT: [13] - SiFiveP600VLD +# CHECK-NEXT: [14] - SiFiveP600VST + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] +# CHECK-NEXT: - - - - 44.00 - - - - - - - - - 472.00 472.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions: +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vlse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vlse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 128.00 vsse8.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsse16.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse32.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse64.v v8, (a0), t0 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s new file mode 100644 index 0000000000000..2671e0bb2f5d6 --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s @@ -0,0 +1,591 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s + +vsetvli zero, zero, e8, mf8, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf4, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf2, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m1, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m2, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m4, ta, ma +vluxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m8, ta, ma +vluxei8.v v8, (a0), v0 + +vsetvli zero, zero, e16, mf4, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, mf2, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m1, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m2, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m4, ta, ma +vluxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m8, ta, ma +vluxei16.v v8, (a0), v0 + +vsetvli zero, zero, e32, mf2, ta, ma +vluxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m1, ta, ma +vluxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m2, ta, ma +vluxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m4, ta, ma +vluxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m8, ta, ma +vluxei32.v v8, (a0), v0 + +vsetvli zero, zero, e64, m1, ta, ma +vluxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m2, ta, ma +vluxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m4, ta, ma +vluxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m8, ta, ma +vluxei64.v v8, (a0), v0 + +vsetvli zero, zero, e8, mf8, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf4, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf2, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m1, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m2, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m4, ta, ma +vloxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m8, ta, ma +vloxei8.v v8, (a0), v0 + +vsetvli zero, zero, e16, mf4, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, mf2, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m1, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m2, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m4, ta, ma +vloxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m8, ta, ma +vloxei16.v v8, (a0), v0 + +vsetvli zero, zero, e32, mf2, ta, ma +vloxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m1, ta, ma +vloxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m2, ta, ma +vloxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m4, ta, ma +vloxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m8, ta, ma +vloxei32.v v8, (a0), v0 + +vsetvli zero, zero, e64, m1, ta, ma +vloxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m2, ta, ma +vloxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m4, ta, ma +vloxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m8, ta, ma +vloxei64.v v8, (a0), v0 + +vsetvli zero, zero, e8, mf8, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf4, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf2, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m1, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m2, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m4, ta, ma +vsuxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m8, ta, ma +vsuxei8.v v8, (a0), v0 + +vsetvli zero, zero, e16, mf4, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, mf2, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m1, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m2, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m4, ta, ma +vsuxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m8, ta, ma +vsuxei16.v v8, (a0), v0 + +vsetvli zero, zero, e32, mf2, ta, ma +vsuxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m1, ta, ma +vsuxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m2, ta, ma +vsuxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m4, ta, ma +vsuxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m8, ta, ma +vsuxei32.v v8, (a0), v0 + +vsetvli zero, zero, e64, m1, ta, ma +vsuxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m2, ta, ma +vsuxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m4, ta, ma +vsuxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m8, ta, ma +vsuxei64.v v8, (a0), v0 + +vsetvli zero, zero, e8, mf8, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf4, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, mf2, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m1, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m2, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m4, ta, ma +vsoxei8.v v8, (a0), v0 +vsetvli zero, zero, e8, m8, ta, ma +vsoxei8.v v8, (a0), v0 + +vsetvli zero, zero, e16, mf4, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, mf2, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m1, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m2, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m4, ta, ma +vsoxei16.v v8, (a0), v0 +vsetvli zero, zero, e16, m8, ta, ma +vsoxei16.v v8, (a0), v0 + +vsetvli zero, zero, e32, mf2, ta, ma +vsoxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m1, ta, ma +vsoxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m2, ta, ma +vsoxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m4, ta, ma +vsoxei32.v v8, (a0), v0 +vsetvli zero, zero, e32, m8, ta, ma +vsoxei32.v v8, (a0), v0 + +vsetvli zero, zero, e64, m1, ta, ma +vsoxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m2, ta, ma +vsoxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m4, ta, ma +vsoxei64.v v8, (a0), v0 +vsetvli zero, zero, e64, m8, ta, ma +vsoxei64.v v8, (a0), v0 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 176 +# CHECK-NEXT: Total Cycles: 1898 +# CHECK-NEXT: Total uOps: 176 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.09 +# CHECK-NEXT: IPC: 0.09 +# CHECK-NEXT: Block RThroughput: 944.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vluxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vluxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vluxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vluxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vluxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vluxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vluxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vloxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vloxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vloxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vloxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vloxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vloxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vloxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsuxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsuxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsuxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: 1 126 128.00 * vsoxei8.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: 1 62 64.00 * vsoxei16.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: 1 30 32.00 * vsoxei32.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: 1 13 2.00 * vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: 1 18 4.00 * vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: 1 22 8.00 * vsoxei64.v v8, (a0), v0 +# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: 1 30 16.00 * vsoxei64.v v8, (a0), v0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFiveP600Div +# CHECK-NEXT: [1] - SiFiveP600FEXQ0 +# CHECK-NEXT: [2] - SiFiveP600FEXQ1 +# CHECK-NEXT: [3] - SiFiveP600FloatDiv +# CHECK-NEXT: [4] - SiFiveP600IEXQ0 +# CHECK-NEXT: [5] - SiFiveP600IEXQ1 +# CHECK-NEXT: [6] - SiFiveP600IEXQ2 +# CHECK-NEXT: [7] - SiFiveP600IEXQ3 +# CHECK-NEXT: [8.0] - SiFiveP600LDST +# CHECK-NEXT: [8.1] - SiFiveP600LDST +# CHECK-NEXT: [9] - SiFiveP600VDiv +# CHECK-NEXT: [10] - SiFiveP600VEXQ0 +# CHECK-NEXT: [11] - SiFiveP600VEXQ1 +# CHECK-NEXT: [12] - SiFiveP600VFloatDiv +# CHECK-NEXT: [13] - SiFiveP600VLD +# CHECK-NEXT: [14] - SiFiveP600VST + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] +# CHECK-NEXT: - - - - 88.00 - - - - - - - - - 944.00 944.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions: +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vluxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vluxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vloxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vloxei16.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei32.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei64.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma +# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei8.v v8, (a0), v0 +# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, 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